ENGR00143575 IPUv3:Align IDMAC BS with DMFC FIFO BS
[efikamx:linux-kernel.git] / drivers / mxc / ipu3 / ipu_common.c
1 /*
2  * Copyright 2005-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3  */
4
5 /*
6  * The code contained herein is licensed under the GNU General Public
7  * License. You may obtain a copy of the GNU General Public License
8  * Version 2 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/gpl-license.html
11  * http://www.gnu.org/copyleft/gpl.html
12  */
13
14 /*!
15  * @file ipu_common.c
16  *
17  * @brief This file contains the IPU driver common API functions.
18  *
19  * @ingroup IPU
20  */
21 #include <linux/types.h>
22 #include <linux/init.h>
23 #include <linux/platform_device.h>
24 #include <linux/err.h>
25 #include <linux/spinlock.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/ipu.h>
30 #include <linux/clk.h>
31 #include <mach/clock.h>
32 #include <mach/hardware.h>
33 #include <mach/mxc_dvfs.h>
34
35 #include "ipu_prv.h"
36 #include "ipu_regs.h"
37 #include "ipu_param_mem.h"
38
39 struct ipu_irq_node {
40         irqreturn_t(*handler) (int, void *);    /*!< the ISR */
41         const char *name;       /*!< device associated with the interrupt */
42         void *dev_id;           /*!< some unique information for the ISR */
43         __u32 flags;            /*!< not used */
44 };
45
46 /* Globals */
47 struct clk *g_ipu_clk;
48 bool g_ipu_clk_enabled;
49 struct clk *g_di_clk[2];
50 struct clk *g_pixel_clk[2];
51 struct clk *g_csi_clk[2];
52 unsigned char g_dc_di_assignment[10];
53 ipu_channel_t g_ipu_csi_channel[2];
54 int g_ipu_irq[2];
55 int g_ipu_hw_rev;
56 bool g_sec_chan_en[24];
57 bool g_thrd_chan_en[24];
58 bool g_chan_is_interlaced[52];
59 uint32_t g_channel_init_mask;
60 uint32_t g_channel_enable_mask;
61 DEFINE_SPINLOCK(ipu_lock);
62 struct device *g_ipu_dev;
63
64 static struct ipu_irq_node ipu_irq_list[IPU_IRQ_COUNT];
65 static const char driver_name[] = "mxc_ipu";
66
67 static int ipu_dc_use_count;
68 static int ipu_dp_use_count;
69 static int ipu_dmfc_use_count;
70 static int ipu_smfc_use_count;
71 static int ipu_ic_use_count;
72 static int ipu_rot_use_count;
73 static int ipu_vdi_use_count;
74 static int ipu_di_use_count[2];
75 static int ipu_csi_use_count[2];
76 /* Set to the follow using IC direct channel, default non */
77 static ipu_channel_t using_ic_dirct_ch;
78
79 /* for power gating */
80 static uint32_t ipu_conf_reg;
81 static uint32_t ic_conf_reg;
82 static uint32_t ipu_cha_db_mode_reg[4];
83 static uint32_t ipu_cha_trb_mode_reg[2];
84 static uint32_t ipu_cha_cur_buf_reg[4];
85 static uint32_t ipu_cha_triple_cur_buf_reg[4];
86 static uint32_t idma_sub_addr_reg[5];
87 static uint32_t idma_enable_reg[2];
88 static uint32_t buf_ready_reg[10];
89
90 u32 *ipu_cm_reg;
91 u32 *ipu_idmac_reg;
92 u32 *ipu_dp_reg;
93 u32 *ipu_ic_reg;
94 u32 *ipu_dc_reg;
95 u32 *ipu_dc_tmpl_reg;
96 u32 *ipu_dmfc_reg;
97 u32 *ipu_di_reg[2];
98 u32 *ipu_smfc_reg;
99 u32 *ipu_csi_reg[2];
100 u32 *ipu_cpmem_base;
101 u32 *ipu_tpmem_base;
102 u32 *ipu_disp_base[2];
103 u32 *ipu_vdi_reg;
104
105 /* Static functions */
106 static irqreturn_t ipu_irq_handler(int irq, void *desc);
107
108 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
109 {
110         return ((uint32_t) ch >> (6 * type)) & 0x3F;
111 };
112
113 static inline int _ipu_is_ic_chan(uint32_t dma_chan)
114 {
115         return ((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) && (dma_chan != 18));
116 }
117
118 static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
119 {
120         return (dma_chan == 14 || dma_chan == 15);
121 }
122
123 /* Either DP BG or DP FG can be graphic window */
124 static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
125 {
126         return (dma_chan == 23 || dma_chan == 27);
127 }
128
129 static inline int _ipu_is_irt_chan(uint32_t dma_chan)
130 {
131         return ((dma_chan >= 45) && (dma_chan <= 50));
132 }
133
134 static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
135 {
136         return ((dma_chan >= 23) && (dma_chan <= 29));
137 }
138
139 static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
140 {
141         return ((dma_chan >= 0) && (dma_chan <= 3));
142 }
143
144 static inline int _ipu_is_trb_chan(uint32_t dma_chan)
145 {
146         return (((dma_chan == 8) || (dma_chan == 9) ||
147                  (dma_chan == 10) || (dma_chan == 13) ||
148                  (dma_chan == 21) || (dma_chan == 23) ||
149                  (dma_chan == 27) || (dma_chan == 28)) &&
150                 (g_ipu_hw_rev >= 2));
151 }
152
153 #define idma_is_valid(ch)       (ch != NO_DMA)
154 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
155 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
156 #define tri_cur_buf_mask(ch)    (idma_mask(ch*2) * 3)
157 #define tri_cur_buf_shift(ch)   (ffs(idma_mask(ch*2)) - 1)
158
159 static void _ipu_pixel_clk_recalc(struct clk *clk)
160 {
161         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
162         if (div == 0)
163                 clk->rate = 0;
164         else
165                 clk->rate = (clk_get_rate(clk->parent) * 16) / div;
166 }
167
168 static unsigned long _ipu_pixel_clk_round_rate(struct clk *clk, unsigned long rate)
169 {
170         u32 div, div1;
171         u32 parent_rate = clk_get_rate(clk->parent) * 16;
172         /*
173          * Calculate divider
174          * Fractional part is 4 bits,
175          * so simply multiply by 2^4 to get fractional part.
176          */
177         div = parent_rate / rate;
178
179         if (div < 0x10)            /* Min DI disp clock divider is 1 */
180                 div = 0x10;
181         if (div & ~0xFEF)
182                 div &= 0xFF8;
183         else {
184                 div1 = div & 0xFE0;
185                 if ((parent_rate / div1 - parent_rate / div) < rate / 4)
186                         div = div1;
187                 else
188                         div &= 0xFF8;
189         }
190         return parent_rate / div;
191 }
192
193 static int _ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
194 {
195         u32 div = (clk_get_rate(clk->parent) * 16) / rate;
196
197         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
198
199         /* Setup pixel clock timing */
200         /* FIXME: needs to be more flexible */
201         /* Down time is half of period */
202         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
203
204         clk->rate = (clk->parent->rate * 16) / div;
205         return 0;
206 }
207
208 static int _ipu_pixel_clk_enable(struct clk *clk)
209 {
210         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
211         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
212         __raw_writel(disp_gen, IPU_DISP_GEN);
213
214         start_dvfs_per();
215
216         return 0;
217 }
218
219 static void _ipu_pixel_clk_disable(struct clk *clk)
220 {
221         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
222         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
223         __raw_writel(disp_gen, IPU_DISP_GEN);
224
225         start_dvfs_per();
226 }
227
228 static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
229 {
230         u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
231
232         if (parent == g_ipu_clk)
233                 di_gen &= ~DI_GEN_DI_CLK_EXT;
234         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
235                 di_gen |= DI_GEN_DI_CLK_EXT;
236         else
237                 return -EINVAL;
238
239         __raw_writel(di_gen, DI_GENERAL(clk->id));
240         _ipu_pixel_clk_recalc(clk);
241         return 0;
242 }
243
244 static struct clk pixel_clk[] = {
245         {
246         .name = "pixel_clk",
247         .id = 0,
248         .recalc = _ipu_pixel_clk_recalc,
249         .set_rate = _ipu_pixel_clk_set_rate,
250         .round_rate = _ipu_pixel_clk_round_rate,
251         .set_parent = _ipu_pixel_clk_set_parent,
252         .enable = _ipu_pixel_clk_enable,
253         .disable = _ipu_pixel_clk_disable,
254         },
255         {
256         .name = "pixel_clk",
257         .id = 1,
258         .recalc = _ipu_pixel_clk_recalc,
259         .set_rate = _ipu_pixel_clk_set_rate,
260         .round_rate = _ipu_pixel_clk_round_rate,
261         .set_parent = _ipu_pixel_clk_set_parent,
262         .enable = _ipu_pixel_clk_enable,
263         .disable = _ipu_pixel_clk_disable,
264         },
265 };
266
267 /*!
268  * This function is called by the driver framework to initialize the IPU
269  * hardware.
270  *
271  * @param       dev     The device structure for the IPU passed in by the
272  *                      driver framework.
273  *
274  * @return      Returns 0 on success or negative error code on error
275  */
276 static int ipu_probe(struct platform_device *pdev)
277 {
278         struct resource *res;
279         struct mxc_ipu_config *plat_data = pdev->dev.platform_data;
280         unsigned long ipu_base;
281
282         spin_lock_init(&ipu_lock);
283
284         g_ipu_hw_rev = plat_data->rev;
285
286         g_ipu_dev = &pdev->dev;
287
288         /* Register IPU interrupts */
289         g_ipu_irq[0] = platform_get_irq(pdev, 0);
290         if (g_ipu_irq[0] < 0)
291                 return -EINVAL;
292
293         if (request_irq(g_ipu_irq[0], ipu_irq_handler, 0, pdev->name, 0) != 0) {
294                 dev_err(g_ipu_dev, "request SYNC interrupt failed\n");
295                 return -EBUSY;
296         }
297         /* Some platforms have 2 IPU interrupts */
298         g_ipu_irq[1] = platform_get_irq(pdev, 1);
299         if (g_ipu_irq[1] >= 0) {
300                 if (request_irq
301                     (g_ipu_irq[1], ipu_irq_handler, 0, pdev->name, 0) != 0) {
302                         dev_err(g_ipu_dev, "request ERR interrupt failed\n");
303                         return -EBUSY;
304                 }
305         }
306
307         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
308         if (IS_ERR(res))
309                 return -ENODEV;
310
311         ipu_base = res->start;
312         if (g_ipu_hw_rev == 3)  /* IPUv3M */
313                 ipu_base += IPUV3M_REG_BASE;
314         else                    /* IPUv3D, v3E, v3EX */
315                 ipu_base += IPU_REG_BASE;
316
317         ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
318         ipu_ic_reg = ioremap(ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
319         ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
320         /* DP Registers are accessed thru the SRM */
321         ipu_dp_reg = ioremap(ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
322         ipu_dc_reg = ioremap(ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
323         ipu_dmfc_reg = ioremap(ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
324         ipu_di_reg[0] = ioremap(ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
325         ipu_di_reg[1] = ioremap(ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
326         ipu_smfc_reg = ioremap(ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
327         ipu_csi_reg[0] = ioremap(ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
328         ipu_csi_reg[1] = ioremap(ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
329         ipu_cpmem_base = ioremap(ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
330         ipu_tpmem_base = ioremap(ipu_base + IPU_TPM_REG_BASE, SZ_64K);
331         ipu_dc_tmpl_reg = ioremap(ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
332         ipu_disp_base[1] = ioremap(ipu_base + IPU_DISP1_BASE, SZ_4K);
333         ipu_vdi_reg = ioremap(ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
334
335         dev_dbg(g_ipu_dev, "IPU VDI Regs = %p\n", ipu_vdi_reg);
336         dev_dbg(g_ipu_dev, "IPU CM Regs = %p\n", ipu_cm_reg);
337         dev_dbg(g_ipu_dev, "IPU IC Regs = %p\n", ipu_ic_reg);
338         dev_dbg(g_ipu_dev, "IPU IDMAC Regs = %p\n", ipu_idmac_reg);
339         dev_dbg(g_ipu_dev, "IPU DP Regs = %p\n", ipu_dp_reg);
340         dev_dbg(g_ipu_dev, "IPU DC Regs = %p\n", ipu_dc_reg);
341         dev_dbg(g_ipu_dev, "IPU DMFC Regs = %p\n", ipu_dmfc_reg);
342         dev_dbg(g_ipu_dev, "IPU DI0 Regs = %p\n", ipu_di_reg[0]);
343         dev_dbg(g_ipu_dev, "IPU DI1 Regs = %p\n", ipu_di_reg[1]);
344         dev_dbg(g_ipu_dev, "IPU SMFC Regs = %p\n", ipu_smfc_reg);
345         dev_dbg(g_ipu_dev, "IPU CSI0 Regs = %p\n", ipu_csi_reg[0]);
346         dev_dbg(g_ipu_dev, "IPU CSI1 Regs = %p\n", ipu_csi_reg[1]);
347         dev_dbg(g_ipu_dev, "IPU CPMem = %p\n", ipu_cpmem_base);
348         dev_dbg(g_ipu_dev, "IPU TPMem = %p\n", ipu_tpmem_base);
349         dev_dbg(g_ipu_dev, "IPU DC Template Mem = %p\n", ipu_dc_tmpl_reg);
350         dev_dbg(g_ipu_dev, "IPU Display Region 1 Mem = %p\n", ipu_disp_base[1]);
351
352         g_pixel_clk[0] = &pixel_clk[0];
353         g_pixel_clk[1] = &pixel_clk[1];
354
355         /* Enable IPU and CSI clocks */
356         /* Get IPU clock freq */
357         g_ipu_clk = clk_get(&pdev->dev, "ipu_clk");
358         dev_dbg(g_ipu_dev, "ipu_clk = %lu\n", clk_get_rate(g_ipu_clk));
359
360         if (plat_data->reset)
361                 plat_data->reset();
362
363         clk_set_parent(g_pixel_clk[0], g_ipu_clk);
364         clk_set_parent(g_pixel_clk[1], g_ipu_clk);
365         clk_enable(g_ipu_clk);
366
367         g_di_clk[0] = plat_data->di_clk[0];
368         g_di_clk[1] = plat_data->di_clk[1];
369
370         g_csi_clk[0] = plat_data->csi_clk[0];
371         g_csi_clk[1] = plat_data->csi_clk[1];
372
373         __raw_writel(0x807FFFFF, IPU_MEM_RST);
374         while (__raw_readl(IPU_MEM_RST) & 0x80000000)
375                 ;
376
377         _ipu_init_dc_mappings();
378
379         /* Enable error interrupts by default */
380         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
381         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
382         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
383         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
384
385         /* DMFC Init */
386         _ipu_dmfc_init(DMFC_NORMAL, 1);
387
388         /* Set sync refresh channels and CSI->mem channel as high priority */
389         __raw_writel(0x18800001L, IDMAC_CHA_PRI(0));
390
391         /* Set MCU_T to divide MCU access window into 2 */
392         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
393
394         clk_disable(g_ipu_clk);
395
396         register_ipu_device();
397
398         return 0;
399 }
400
401 int ipu_remove(struct platform_device *pdev)
402 {
403         if (g_ipu_irq[0])
404                 free_irq(g_ipu_irq[0], 0);
405         if (g_ipu_irq[1])
406                 free_irq(g_ipu_irq[1], 0);
407
408         clk_put(g_ipu_clk);
409
410         iounmap(ipu_cm_reg);
411         iounmap(ipu_ic_reg);
412         iounmap(ipu_idmac_reg);
413         iounmap(ipu_dc_reg);
414         iounmap(ipu_dp_reg);
415         iounmap(ipu_dmfc_reg);
416         iounmap(ipu_di_reg[0]);
417         iounmap(ipu_di_reg[1]);
418         iounmap(ipu_smfc_reg);
419         iounmap(ipu_csi_reg[0]);
420         iounmap(ipu_csi_reg[1]);
421         iounmap(ipu_cpmem_base);
422         iounmap(ipu_tpmem_base);
423         iounmap(ipu_dc_tmpl_reg);
424         iounmap(ipu_disp_base[1]);
425         iounmap(ipu_vdi_reg);
426
427         return 0;
428 }
429
430 void ipu_dump_registers(void)
431 {
432         printk(KERN_DEBUG "IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
433         printk(KERN_DEBUG "IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
434         printk(KERN_DEBUG "IDMAC_CHA_EN1 = \t0x%08X\n",
435                __raw_readl(IDMAC_CHA_EN(0)));
436         printk(KERN_DEBUG "IDMAC_CHA_EN2 = \t0x%08X\n",
437                __raw_readl(IDMAC_CHA_EN(32)));
438         printk(KERN_DEBUG "IDMAC_CHA_PRI1 = \t0x%08X\n",
439                __raw_readl(IDMAC_CHA_PRI(0)));
440         printk(KERN_DEBUG "IDMAC_CHA_PRI2 = \t0x%08X\n",
441                __raw_readl(IDMAC_CHA_PRI(32)));
442         printk(KERN_DEBUG "IDMAC_BAND_EN1 = \t0x%08X\n",
443                __raw_readl(IDMAC_BAND_EN(0)));
444         printk(KERN_DEBUG "IDMAC_BAND_EN2 = \t0x%08X\n",
445                __raw_readl(IDMAC_BAND_EN(32)));
446         printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
447                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
448         printk(KERN_DEBUG "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
449                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
450         if (g_ipu_hw_rev >= 2) {
451                 printk(KERN_DEBUG "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
452                        __raw_readl(IPU_CHA_TRB_MODE_SEL(0)));
453                 printk(KERN_DEBUG "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
454                        __raw_readl(IPU_CHA_TRB_MODE_SEL(32)));
455         }
456         printk(KERN_DEBUG "DMFC_WR_CHAN = \t0x%08X\n",
457                __raw_readl(DMFC_WR_CHAN));
458         printk(KERN_DEBUG "DMFC_WR_CHAN_DEF = \t0x%08X\n",
459                __raw_readl(DMFC_WR_CHAN_DEF));
460         printk(KERN_DEBUG "DMFC_DP_CHAN = \t0x%08X\n",
461                __raw_readl(DMFC_DP_CHAN));
462         printk(KERN_DEBUG "DMFC_DP_CHAN_DEF = \t0x%08X\n",
463                __raw_readl(DMFC_DP_CHAN_DEF));
464         printk(KERN_DEBUG "DMFC_IC_CTRL = \t0x%08X\n",
465                __raw_readl(DMFC_IC_CTRL));
466         printk(KERN_DEBUG "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
467                __raw_readl(IPU_FS_PROC_FLOW1));
468         printk(KERN_DEBUG "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
469                __raw_readl(IPU_FS_PROC_FLOW2));
470         printk(KERN_DEBUG "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
471                __raw_readl(IPU_FS_PROC_FLOW3));
472         printk(KERN_DEBUG "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
473                __raw_readl(IPU_FS_DISP_FLOW1));
474 }
475
476 /*!
477  * This function is called to initialize a logical IPU channel.
478  *
479  * @param       channel Input parameter for the logical channel ID to init.
480  *
481  * @param       params  Input parameter containing union of channel
482  *                      initialization parameters.
483  *
484  * @return      Returns 0 on success or negative error code on fail
485  */
486 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
487 {
488         int ret = 0;
489         uint32_t ipu_conf;
490         uint32_t reg;
491         unsigned long lock_flags;
492
493         dev_dbg(g_ipu_dev, "init channel = %d\n", IPU_CHAN_ID(channel));
494
495         /* re-enable error interrupts every time a channel is initialized */
496         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(5));
497         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(6));
498         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(9));
499         __raw_writel(0xFFFFFFFF, IPU_INT_CTRL(10));
500
501         if (g_ipu_clk_enabled == false) {
502                 stop_dvfs_per();
503                 g_ipu_clk_enabled = true;
504                 clk_enable(g_ipu_clk);
505         }
506
507         spin_lock_irqsave(&ipu_lock, lock_flags);
508
509         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
510                 dev_err(g_ipu_dev, "Warning: channel already initialized %d\n",
511                         IPU_CHAN_ID(channel));
512                 ret = -EINVAL;
513                 goto err;
514         }
515
516         ipu_conf = __raw_readl(IPU_CONF);
517
518         switch (channel) {
519         case CSI_MEM0:
520         case CSI_MEM1:
521         case CSI_MEM2:
522         case CSI_MEM3:
523                 if (params->csi_mem.csi > 1) {
524                         ret = -EINVAL;
525                         goto err;
526                 }
527
528                 if (params->csi_mem.interlaced)
529                         g_chan_is_interlaced[channel_2_dma(channel,
530                                 IPU_OUTPUT_BUFFER)] = true;
531                 else
532                         g_chan_is_interlaced[channel_2_dma(channel,
533                                 IPU_OUTPUT_BUFFER)] = false;
534
535                 ipu_smfc_use_count++;
536                 g_ipu_csi_channel[params->csi_mem.csi] = channel;
537
538                 /*SMFC setting*/
539                 if (params->csi_mem.mipi_en) {
540                         ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
541                                 params->csi_mem.csi));
542                         _ipu_smfc_init(channel, params->csi_mem.mipi_id,
543                                 params->csi_mem.csi);
544                 } else {
545                         ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
546                                 params->csi_mem.csi));
547                         _ipu_smfc_init(channel, 0, params->csi_mem.csi);
548                 }
549
550                 /*CSI data (include compander) dest*/
551                 _ipu_csi_init(channel, params->csi_mem.csi);
552                 break;
553         case CSI_PRP_ENC_MEM:
554                 if (params->csi_prp_enc_mem.csi > 1) {
555                         ret = -EINVAL;
556                         goto err;
557                 }
558                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
559                         ret = -EINVAL;
560                         goto err;
561                 }
562                 using_ic_dirct_ch = CSI_PRP_ENC_MEM;
563
564                 ipu_ic_use_count++;
565                 g_ipu_csi_channel[params->csi_prp_enc_mem.csi] = channel;
566
567                 /*Without SMFC, CSI only support parallel data source*/
568                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
569                         params->csi_prp_enc_mem.csi));
570
571                 /*CSI0/1 feed into IC*/
572                 ipu_conf &= ~IPU_CONF_IC_INPUT;
573                 if (params->csi_prp_enc_mem.csi)
574                         ipu_conf |= IPU_CONF_CSI_SEL;
575                 else
576                         ipu_conf &= ~IPU_CONF_CSI_SEL;
577
578                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
579                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
580                 __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
581
582                 /*CSI data (include compander) dest*/
583                 _ipu_csi_init(channel, params->csi_prp_enc_mem.csi);
584                 _ipu_ic_init_prpenc(params, true);
585                 break;
586         case CSI_PRP_VF_MEM:
587                 if (params->csi_prp_vf_mem.csi > 1) {
588                         ret = -EINVAL;
589                         goto err;
590                 }
591                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) {
592                         ret = -EINVAL;
593                         goto err;
594                 }
595                 using_ic_dirct_ch = CSI_PRP_VF_MEM;
596
597                 ipu_ic_use_count++;
598                 g_ipu_csi_channel[params->csi_prp_vf_mem.csi] = channel;
599
600                 /*Without SMFC, CSI only support parallel data source*/
601                 ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
602                         params->csi_prp_vf_mem.csi));
603
604                 /*CSI0/1 feed into IC*/
605                 ipu_conf &= ~IPU_CONF_IC_INPUT;
606                 if (params->csi_prp_vf_mem.csi)
607                         ipu_conf |= IPU_CONF_CSI_SEL;
608                 else
609                         ipu_conf &= ~IPU_CONF_CSI_SEL;
610
611                 /*PRP skip buffer in memory, only valid when RWS_EN is true*/
612                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
613                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
614
615                 /*CSI data (include compander) dest*/
616                 _ipu_csi_init(channel, params->csi_prp_vf_mem.csi);
617                 _ipu_ic_init_prpvf(params, true);
618                 break;
619         case MEM_PRP_VF_MEM:
620                 ipu_ic_use_count++;
621                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
622                 __raw_writel(reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
623
624                 if (params->mem_prp_vf_mem.graphics_combine_en)
625                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
626                 if (params->mem_prp_vf_mem.alpha_chan_en)
627                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
628
629                 _ipu_ic_init_prpvf(params, false);
630                 break;
631         case MEM_VDI_PRP_VF_MEM:
632                 if ((using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
633                      (using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
634                         ret = -EINVAL;
635                         goto err;
636                 }
637                 using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
638                 ipu_ic_use_count++;
639                 ipu_vdi_use_count++;
640                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
641                 reg &= ~FS_VDI_SRC_SEL_MASK;
642                 __raw_writel(reg , IPU_FS_PROC_FLOW1);
643
644                 if (params->mem_prp_vf_mem.graphics_combine_en)
645                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
646                 _ipu_ic_init_prpvf(params, false);
647                 _ipu_vdi_init(channel, params);
648                 break;
649         case MEM_VDI_PRP_VF_MEM_P:
650                 _ipu_vdi_init(channel, params);
651                 break;
652         case MEM_VDI_PRP_VF_MEM_N:
653                 _ipu_vdi_init(channel, params);
654                 break;
655         case MEM_ROT_VF_MEM:
656                 ipu_ic_use_count++;
657                 ipu_rot_use_count++;
658                 _ipu_ic_init_rotate_vf(params);
659                 break;
660         case MEM_PRP_ENC_MEM:
661                 ipu_ic_use_count++;
662                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
663                 __raw_writel(reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
664                 _ipu_ic_init_prpenc(params, false);
665                 break;
666         case MEM_ROT_ENC_MEM:
667                 ipu_ic_use_count++;
668                 ipu_rot_use_count++;
669                 _ipu_ic_init_rotate_enc(params);
670                 break;
671         case MEM_PP_MEM:
672                 if (params->mem_pp_mem.graphics_combine_en)
673                         g_sec_chan_en[IPU_CHAN_ID(channel)] = true;
674                 if (params->mem_pp_mem.alpha_chan_en)
675                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
676                 _ipu_ic_init_pp(params);
677                 ipu_ic_use_count++;
678                 break;
679         case MEM_ROT_PP_MEM:
680                 _ipu_ic_init_rotate_pp(params);
681                 ipu_ic_use_count++;
682                 ipu_rot_use_count++;
683                 break;
684         case MEM_DC_SYNC:
685                 if (params->mem_dc_sync.di > 1) {
686                         ret = -EINVAL;
687                         goto err;
688                 }
689
690                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
691                 _ipu_dc_init(1, params->mem_dc_sync.di,
692                              params->mem_dc_sync.interlaced,
693                              params->mem_dc_sync.out_pixel_fmt);
694                 ipu_di_use_count[params->mem_dc_sync.di]++;
695                 ipu_dc_use_count++;
696                 ipu_dmfc_use_count++;
697                 break;
698         case MEM_BG_SYNC:
699                 if (params->mem_dp_bg_sync.di > 1) {
700                         ret = -EINVAL;
701                         goto err;
702                 }
703
704                 if (params->mem_dp_bg_sync.alpha_chan_en)
705                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
706
707                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
708                 _ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
709                              params->mem_dp_bg_sync.out_pixel_fmt);
710                 _ipu_dc_init(5, params->mem_dp_bg_sync.di,
711                              params->mem_dp_bg_sync.interlaced,
712                              params->mem_dp_bg_sync.out_pixel_fmt);
713                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
714                 ipu_dc_use_count++;
715                 ipu_dp_use_count++;
716                 ipu_dmfc_use_count++;
717                 break;
718         case MEM_FG_SYNC:
719                 _ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
720                              params->mem_dp_fg_sync.out_pixel_fmt);
721
722                 if (params->mem_dp_fg_sync.alpha_chan_en)
723                         g_thrd_chan_en[IPU_CHAN_ID(channel)] = true;
724
725                 ipu_dc_use_count++;
726                 ipu_dp_use_count++;
727                 ipu_dmfc_use_count++;
728                 break;
729         case DIRECT_ASYNC0:
730                 if (params->direct_async.di > 1) {
731                         ret = -EINVAL;
732                         goto err;
733                 }
734
735                 g_dc_di_assignment[8] = params->direct_async.di;
736                 _ipu_dc_init(8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
737                 ipu_di_use_count[params->direct_async.di]++;
738                 ipu_dc_use_count++;
739                 break;
740         case DIRECT_ASYNC1:
741                 if (params->direct_async.di > 1) {
742                         ret = -EINVAL;
743                         goto err;
744                 }
745
746                 g_dc_di_assignment[9] = params->direct_async.di;
747                 _ipu_dc_init(9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
748                 ipu_di_use_count[params->direct_async.di]++;
749                 ipu_dc_use_count++;
750                 break;
751         default:
752                 dev_err(g_ipu_dev, "Missing channel initialization\n");
753                 ret = -EINVAL;
754                 goto err;
755         }
756
757         /* Enable IPU sub module */
758         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
759
760         __raw_writel(ipu_conf, IPU_CONF);
761
762 err:
763         spin_unlock_irqrestore(&ipu_lock, lock_flags);
764         return ret;
765 }
766 EXPORT_SYMBOL(ipu_init_channel);
767
768 /*!
769  * This function is called to uninitialize a logical IPU channel.
770  *
771  * @param       channel Input parameter for the logical channel ID to uninit.
772  */
773 void ipu_uninit_channel(ipu_channel_t channel)
774 {
775         unsigned long lock_flags;
776         uint32_t reg;
777         uint32_t in_dma, out_dma = 0;
778         uint32_t ipu_conf;
779
780         spin_lock_irqsave(&ipu_lock, lock_flags);
781
782         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
783                 dev_info(g_ipu_dev, "Channel already uninitialized %d\n",
784                         IPU_CHAN_ID(channel));
785                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
786                 return;
787         }
788
789         /* Make sure channel is disabled */
790         /* Get input and output dma channels */
791         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
792         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
793
794         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
795             idma_is_set(IDMAC_CHA_EN, out_dma)) {
796                 dev_err(g_ipu_dev,
797                         "Channel %d is not disabled, disable first\n",
798                         IPU_CHAN_ID(channel));
799                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
800                 return;
801         }
802
803         ipu_conf = __raw_readl(IPU_CONF);
804
805         /* Reset the double buffer */
806         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
807         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
808         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
809         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
810
811         /* Reset the triple buffer */
812         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(in_dma));
813         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
814         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(out_dma));
815         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
816
817         if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
818                 g_sec_chan_en[IPU_CHAN_ID(channel)] = false;
819                 g_thrd_chan_en[IPU_CHAN_ID(channel)] = false;
820         }
821
822         switch (channel) {
823         case CSI_MEM0:
824         case CSI_MEM1:
825         case CSI_MEM2:
826         case CSI_MEM3:
827                 ipu_smfc_use_count--;
828                 if (g_ipu_csi_channel[0] == channel) {
829                         g_ipu_csi_channel[0] = CHAN_NONE;
830                 } else if (g_ipu_csi_channel[1] == channel) {
831                         g_ipu_csi_channel[1] = CHAN_NONE;
832                 }
833                 break;
834         case CSI_PRP_ENC_MEM:
835                 ipu_ic_use_count--;
836                 if (using_ic_dirct_ch == CSI_PRP_ENC_MEM)
837                         using_ic_dirct_ch = 0;
838                 _ipu_ic_uninit_prpenc();
839                 if (g_ipu_csi_channel[0] == channel) {
840                         g_ipu_csi_channel[0] = CHAN_NONE;
841                 } else if (g_ipu_csi_channel[1] == channel) {
842                         g_ipu_csi_channel[1] = CHAN_NONE;
843                 }
844                 break;
845         case CSI_PRP_VF_MEM:
846                 ipu_ic_use_count--;
847                 if (using_ic_dirct_ch == CSI_PRP_VF_MEM)
848                         using_ic_dirct_ch = 0;
849                 _ipu_ic_uninit_prpvf();
850                 if (g_ipu_csi_channel[0] == channel) {
851                         g_ipu_csi_channel[0] = CHAN_NONE;
852                 } else if (g_ipu_csi_channel[1] == channel) {
853                         g_ipu_csi_channel[1] = CHAN_NONE;
854                 }
855                 break;
856         case MEM_PRP_VF_MEM:
857                 ipu_ic_use_count--;
858                 _ipu_ic_uninit_prpvf();
859                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
860                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
861                 break;
862         case MEM_VDI_PRP_VF_MEM:
863                 ipu_ic_use_count--;
864                 ipu_vdi_use_count--;
865                 if (using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
866                         using_ic_dirct_ch = 0;
867                 _ipu_ic_uninit_prpvf();
868                 _ipu_vdi_uninit();
869                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
870                 __raw_writel(reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
871                 break;
872         case MEM_VDI_PRP_VF_MEM_P:
873         case MEM_VDI_PRP_VF_MEM_N:
874                 break;
875         case MEM_ROT_VF_MEM:
876                 ipu_rot_use_count--;
877                 ipu_ic_use_count--;
878                 _ipu_ic_uninit_rotate_vf();
879                 break;
880         case MEM_PRP_ENC_MEM:
881                 ipu_ic_use_count--;
882                 _ipu_ic_uninit_prpenc();
883                 reg = __raw_readl(IPU_FS_PROC_FLOW1);
884                 __raw_writel(reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
885                 break;
886         case MEM_ROT_ENC_MEM:
887                 ipu_rot_use_count--;
888                 ipu_ic_use_count--;
889                 _ipu_ic_uninit_rotate_enc();
890                 break;
891         case MEM_PP_MEM:
892                 ipu_ic_use_count--;
893                 _ipu_ic_uninit_pp();
894                 break;
895         case MEM_ROT_PP_MEM:
896                 ipu_rot_use_count--;
897                 ipu_ic_use_count--;
898                 _ipu_ic_uninit_rotate_pp();
899                 break;
900         case MEM_DC_SYNC:
901                 _ipu_dc_uninit(1);
902                 ipu_di_use_count[g_dc_di_assignment[1]]--;
903                 ipu_dc_use_count--;
904                 ipu_dmfc_use_count--;
905                 break;
906         case MEM_BG_SYNC:
907                 _ipu_dp_uninit(channel);
908                 _ipu_dc_uninit(5);
909                 ipu_di_use_count[g_dc_di_assignment[5]]--;
910                 ipu_dc_use_count--;
911                 ipu_dp_use_count--;
912                 ipu_dmfc_use_count--;
913                 break;
914         case MEM_FG_SYNC:
915                 _ipu_dp_uninit(channel);
916                 ipu_dc_use_count--;
917                 ipu_dp_use_count--;
918                 ipu_dmfc_use_count--;
919                 break;
920         case DIRECT_ASYNC0:
921                 _ipu_dc_uninit(8);
922                 ipu_di_use_count[g_dc_di_assignment[8]]--;
923                 ipu_dc_use_count--;
924                 break;
925         case DIRECT_ASYNC1:
926                 _ipu_dc_uninit(9);
927                 ipu_di_use_count[g_dc_di_assignment[9]]--;
928                 ipu_dc_use_count--;
929                 break;
930         default:
931                 break;
932         }
933
934         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
935
936         if (ipu_ic_use_count == 0)
937                 ipu_conf &= ~IPU_CONF_IC_EN;
938         if (ipu_vdi_use_count == 0) {
939                 ipu_conf &= ~IPU_CONF_ISP_EN;
940                 ipu_conf &= ~IPU_CONF_VDI_EN;
941                 ipu_conf &= ~IPU_CONF_IC_INPUT;
942         }
943         if (ipu_rot_use_count == 0)
944                 ipu_conf &= ~IPU_CONF_ROT_EN;
945         if (ipu_dc_use_count == 0)
946                 ipu_conf &= ~IPU_CONF_DC_EN;
947         if (ipu_dp_use_count == 0)
948                 ipu_conf &= ~IPU_CONF_DP_EN;
949         if (ipu_dmfc_use_count == 0)
950                 ipu_conf &= ~IPU_CONF_DMFC_EN;
951         if (ipu_di_use_count[0] == 0) {
952                 ipu_conf &= ~IPU_CONF_DI0_EN;
953         }
954         if (ipu_di_use_count[1] == 0) {
955                 ipu_conf &= ~IPU_CONF_DI1_EN;
956         }
957         if (ipu_smfc_use_count == 0)
958                 ipu_conf &= ~IPU_CONF_SMFC_EN;
959
960         __raw_writel(ipu_conf, IPU_CONF);
961
962         spin_unlock_irqrestore(&ipu_lock, lock_flags);
963
964         if (ipu_conf == 0) {
965                 clk_disable(g_ipu_clk);
966                 g_ipu_clk_enabled = false;
967         }
968
969         WARN_ON(ipu_ic_use_count < 0);
970         WARN_ON(ipu_vdi_use_count < 0);
971         WARN_ON(ipu_rot_use_count < 0);
972         WARN_ON(ipu_dc_use_count < 0);
973         WARN_ON(ipu_dp_use_count < 0);
974         WARN_ON(ipu_dmfc_use_count < 0);
975         WARN_ON(ipu_smfc_use_count < 0);
976 }
977 EXPORT_SYMBOL(ipu_uninit_channel);
978
979 /*!
980  * This function is called to initialize buffer(s) for logical IPU channel.
981  *
982  * @param       channel         Input parameter for the logical channel ID.
983  *
984  * @param       type            Input parameter which buffer to initialize.
985  *
986  * @param       pixel_fmt       Input parameter for pixel format of buffer.
987  *                              Pixel format is a FOURCC ASCII code.
988  *
989  * @param       width           Input parameter for width of buffer in pixels.
990  *
991  * @param       height          Input parameter for height of buffer in pixels.
992  *
993  * @param       stride          Input parameter for stride length of buffer
994  *                              in pixels.
995  *
996  * @param       rot_mode        Input parameter for rotation setting of buffer.
997  *                              A rotation setting other than
998  *                              IPU_ROTATE_VERT_FLIP
999  *                              should only be used for input buffers of
1000  *                              rotation channels.
1001  *
1002  * @param       phyaddr_0       Input parameter buffer 0 physical address.
1003  *
1004  * @param       phyaddr_1       Input parameter buffer 1 physical address.
1005  *                              Setting this to a value other than NULL enables
1006  *                              double buffering mode.
1007  *
1008  * @param       phyaddr_2       Input parameter buffer 2 physical address.
1009  *                              Setting this to a value other than NULL enables
1010  *                              triple buffering mode, phyaddr_1 should not be
1011  *                              NULL then.
1012  *
1013  * @param       u               private u offset for additional cropping,
1014  *                              zero if not used.
1015  *
1016  * @param       v               private v offset for additional cropping,
1017  *                              zero if not used.
1018  *
1019  * @return      Returns 0 on success or negative error code on fail
1020  */
1021 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
1022                                 uint32_t pixel_fmt,
1023                                 uint16_t width, uint16_t height,
1024                                 uint32_t stride,
1025                                 ipu_rotate_mode_t rot_mode,
1026                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
1027                                 dma_addr_t phyaddr_2,
1028                                 uint32_t u, uint32_t v)
1029 {
1030         unsigned long lock_flags;
1031         uint32_t reg;
1032         uint32_t dma_chan;
1033         uint32_t burst_size;
1034
1035         dma_chan = channel_2_dma(channel, type);
1036         if (!idma_is_valid(dma_chan))
1037                 return -EINVAL;
1038
1039         if (stride < width * bytes_per_pixel(pixel_fmt))
1040                 stride = width * bytes_per_pixel(pixel_fmt);
1041
1042         if (stride % 4) {
1043                 dev_err(g_ipu_dev,
1044                         "Stride not 32-bit aligned, stride = %d\n", stride);
1045                 return -EINVAL;
1046         }
1047         /* IC & IRT channels' width must be multiple of 8 pixels */
1048         if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
1049                 && (width % 8)) {
1050                 dev_err(g_ipu_dev, "Width must be 8 pixel multiple\n");
1051                 return -EINVAL;
1052         }
1053
1054         /* IPUv3EX and IPUv3M support triple buffer */
1055         if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
1056                 dev_err(g_ipu_dev, "Chan%d doesn't support triple buffer "
1057                                    "mode\n", dma_chan);
1058                 return -EINVAL;
1059         }
1060         if (!phyaddr_1 && phyaddr_2) {
1061                 dev_err(g_ipu_dev, "Chan%d's buf1 physical addr is NULL for "
1062                                    "triple buffer mode\n", dma_chan);
1063                 return -EINVAL;
1064         }
1065
1066         /* Build parameter memory data for DMA channel */
1067         _ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
1068                            phyaddr_0, phyaddr_1, phyaddr_2);
1069
1070         /* Set correlative channel parameter of local alpha channel */
1071         if ((_ipu_is_ic_graphic_chan(dma_chan) ||
1072              _ipu_is_dp_graphic_chan(dma_chan)) &&
1073             (g_thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
1074                 _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, true);
1075                 _ipu_ch_param_set_alpha_buffer_memory(dma_chan);
1076                 _ipu_ch_param_set_alpha_condition_read(dma_chan);
1077                 /* fix alpha width as 8 and burst size as 16*/
1078                 _ipu_ch_params_set_alpha_width(dma_chan, 8);
1079                 _ipu_ch_param_set_burst_size(dma_chan, 16);
1080         } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
1081                    ipu_pixel_format_has_alpha(pixel_fmt))
1082                 _ipu_ch_param_set_alpha_use_separate_channel(dma_chan, false);
1083
1084         if (rot_mode)
1085                 _ipu_ch_param_set_rotation(dma_chan, rot_mode);
1086
1087         /* IC and ROT channels have restriction of 8 or 16 pix burst length */
1088         if (_ipu_is_ic_chan(dma_chan)) {
1089                 if ((width % 16) == 0)
1090                         _ipu_ch_param_set_burst_size(dma_chan, 16);
1091                 else
1092                         _ipu_ch_param_set_burst_size(dma_chan, 8);
1093         } else if (_ipu_is_irt_chan(dma_chan)) {
1094                 _ipu_ch_param_set_burst_size(dma_chan, 8);
1095                 _ipu_ch_param_set_block_mode(dma_chan);
1096         } else if (_ipu_is_dmfc_chan(dma_chan)) {
1097                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1098                 spin_lock_irqsave(&ipu_lock, lock_flags);
1099                 _ipu_dmfc_set_wait4eot(dma_chan, width);
1100                 _ipu_dmfc_set_burst_size(dma_chan, burst_size);
1101                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
1102         }
1103
1104         if (_ipu_chan_is_interlaced(channel) ||
1105                 g_chan_is_interlaced[dma_chan]) {
1106                 _ipu_ch_param_set_interlaced_scan(dma_chan);
1107         }
1108
1109         if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan)) {
1110                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1111                 _ipu_ic_idma_init(dma_chan, width, height, burst_size,
1112                         rot_mode);
1113         } else if (_ipu_is_smfc_chan(dma_chan)) {
1114                 burst_size = _ipu_ch_param_get_burst_size(dma_chan);
1115                 if ((pixel_fmt == IPU_PIX_FMT_GENERIC) &&
1116                         ((_ipu_ch_param_get_bpp(dma_chan) == 5) ||
1117                         (_ipu_ch_param_get_bpp(dma_chan) == 3)))
1118                         burst_size = burst_size >> 4;
1119                 else
1120                         burst_size = burst_size >> 2;
1121                 _ipu_smfc_set_burst_size(channel, burst_size-1);
1122         }
1123
1124         if (idma_is_set(IDMAC_CHA_PRI, dma_chan) && !cpu_is_mx53())
1125                 _ipu_ch_param_set_high_priority(dma_chan);
1126
1127         _ipu_ch_param_dump(dma_chan);
1128
1129         spin_lock_irqsave(&ipu_lock, lock_flags);
1130         if (phyaddr_2 && g_ipu_hw_rev >= 2) {
1131                 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
1132                 reg &= ~idma_mask(dma_chan);
1133                 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1134
1135                 reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
1136                 reg |= idma_mask(dma_chan);
1137                 __raw_writel(reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1138
1139                 /* Set IDMAC third buffer's cpmem number */
1140                 /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
1141                 __raw_writel(0x00444047L, IDMAC_SUB_ADDR_4);
1142                 __raw_writel(0x46004241L, IDMAC_SUB_ADDR_3);
1143                 __raw_writel(0x00000045L, IDMAC_SUB_ADDR_1);
1144
1145                 /* Reset to buffer 0 */
1146                 __raw_writel(tri_cur_buf_mask(dma_chan),
1147                                 IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
1148         } else {
1149                 reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
1150                 reg &= ~idma_mask(dma_chan);
1151                 __raw_writel(reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
1152
1153                 reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
1154                 if (phyaddr_1)
1155                         reg |= idma_mask(dma_chan);
1156                 else
1157                         reg &= ~idma_mask(dma_chan);
1158                 __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
1159
1160                 /* Reset to buffer 0 */
1161                 __raw_writel(idma_mask(dma_chan),
1162                                 IPU_CHA_CUR_BUF(dma_chan));
1163
1164         }
1165         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1166
1167         return 0;
1168 }
1169 EXPORT_SYMBOL(ipu_init_channel_buffer);
1170
1171 /*!
1172  * This function is called to update the physical address of a buffer for
1173  * a logical IPU channel.
1174  *
1175  * @param       channel         Input parameter for the logical channel ID.
1176  *
1177  * @param       type            Input parameter which buffer to initialize.
1178  *
1179  * @param       bufNum          Input parameter for buffer number to update.
1180  *                              0 or 1 are the only valid values.
1181  *
1182  * @param       phyaddr         Input parameter buffer physical address.
1183  *
1184  * @return      This function returns 0 on success or negative error code on
1185  *              fail. This function will fail if the buffer is set to ready.
1186  */
1187 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
1188                                   uint32_t bufNum, dma_addr_t phyaddr)
1189 {
1190         uint32_t reg;
1191         int ret = 0;
1192         unsigned long lock_flags;
1193         uint32_t dma_chan = channel_2_dma(channel, type);
1194         if (dma_chan == IDMA_CHAN_INVALID)
1195                 return -EINVAL;
1196
1197         spin_lock_irqsave(&ipu_lock, lock_flags);
1198
1199         if (bufNum == 0)
1200                 reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
1201         else if (bufNum == 1)
1202                 reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
1203         else
1204                 reg = __raw_readl(IPU_CHA_BUF2_RDY(dma_chan));
1205
1206         if ((reg & idma_mask(dma_chan)) == 0)
1207                 _ipu_ch_param_set_buffer(dma_chan, bufNum, phyaddr);
1208         else
1209                 ret = -EACCES;
1210
1211         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1212         return ret;
1213 }
1214 EXPORT_SYMBOL(ipu_update_channel_buffer);
1215
1216
1217 /*!
1218  * This function is called to initialize a buffer for logical IPU channel.
1219  *
1220  * @param       channel         Input parameter for the logical channel ID.
1221  *
1222  * @param       type            Input parameter which buffer to initialize.
1223  *
1224  * @param       pixel_fmt       Input parameter for pixel format of buffer.
1225  *                              Pixel format is a FOURCC ASCII code.
1226  *
1227  * @param       width           Input parameter for width of buffer in pixels.
1228  *
1229  * @param       height          Input parameter for height of buffer in pixels.
1230  *
1231  * @param       stride          Input parameter for stride length of buffer
1232  *                              in pixels.
1233  *
1234  * @param       u               predefined private u offset for additional cropping,
1235  *                                                              zero if not used.
1236  *
1237  * @param       v               predefined private v offset for additional cropping,
1238  *                                                              zero if not used.
1239  *
1240  * @param                       vertical_offset vertical offset for Y coordinate
1241  *                                                              in the existed frame
1242  *
1243  *
1244  * @param                       horizontal_offset horizontal offset for X coordinate
1245  *                                                              in the existed frame
1246  *
1247  *
1248  * @return      Returns 0 on success or negative error code on fail
1249  *              This function will fail if any buffer is set to ready.
1250  */
1251
1252 int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type,
1253                                 uint32_t pixel_fmt,
1254                                 uint16_t width, uint16_t height,
1255                                 uint32_t stride,
1256                                 uint32_t u, uint32_t v,
1257                                 uint32_t vertical_offset, uint32_t horizontal_offset)
1258 {
1259         int ret = 0;
1260         unsigned long lock_flags;
1261         uint32_t dma_chan = channel_2_dma(channel, type);
1262
1263         if (dma_chan == IDMA_CHAN_INVALID)
1264                 return -EINVAL;
1265
1266         spin_lock_irqsave(&ipu_lock, lock_flags);
1267
1268         if ((__raw_readl(IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1269             (__raw_readl(IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
1270             ((__raw_readl(IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
1271              (__raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
1272              _ipu_is_trb_chan(dma_chan)))
1273                 ret = -EACCES;
1274         else
1275                 _ipu_ch_offset_update(dma_chan, pixel_fmt, width, height, stride,
1276                                       u, v, 0, vertical_offset, horizontal_offset);
1277
1278         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1279         return ret;
1280 }
1281 EXPORT_SYMBOL(ipu_update_channel_offset);
1282
1283
1284 /*!
1285  * This function is called to set a channel's buffer as ready.
1286  *
1287  * @param       channel         Input parameter for the logical channel ID.
1288  *
1289  * @param       type            Input parameter which buffer to initialize.
1290  *
1291  * @param       bufNum          Input parameter for which buffer number set to
1292  *                              ready state.
1293  *
1294  * @return      Returns 0 on success or negative error code on fail
1295  */
1296 int32_t ipu_select_buffer(ipu_channel_t channel, ipu_buffer_t type,
1297                           uint32_t bufNum)
1298 {
1299         uint32_t dma_chan = channel_2_dma(channel, type);
1300         unsigned long lock_flags;
1301
1302         if (dma_chan == IDMA_CHAN_INVALID)
1303                 return -EINVAL;
1304
1305         /* Mark buffer to be ready. */
1306         spin_lock_irqsave(&ipu_lock, lock_flags);
1307         if (bufNum == 0)
1308                 __raw_writel(idma_mask(dma_chan),
1309                              IPU_CHA_BUF0_RDY(dma_chan));
1310         else if (bufNum == 1)
1311                 __raw_writel(idma_mask(dma_chan),
1312                              IPU_CHA_BUF1_RDY(dma_chan));
1313         else
1314                 __raw_writel(idma_mask(dma_chan),
1315                              IPU_CHA_BUF2_RDY(dma_chan));
1316         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1317         return 0;
1318 }
1319 EXPORT_SYMBOL(ipu_select_buffer);
1320
1321 /*!
1322  * This function is called to set a channel's buffer as ready.
1323  *
1324  * @param       bufNum          Input parameter for which buffer number set to
1325  *                              ready state.
1326  *
1327  * @return      Returns 0 on success or negative error code on fail
1328  */
1329 int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum)
1330 {
1331
1332         uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
1333         uint32_t mask_bit =
1334                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
1335                 idma_mask(dma_chan)|
1336                 idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
1337         unsigned long lock_flags;
1338
1339         /* Mark buffers to be ready. */
1340         spin_lock_irqsave(&ipu_lock, lock_flags);
1341         if (bufNum == 0)
1342                 __raw_writel(mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
1343         else
1344                 __raw_writel(mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
1345         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1346         return 0;
1347 }
1348 EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
1349
1350 #define NA      -1
1351 static int proc_dest_sel[] = {
1352         0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
1353         0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
1354 static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
1355   NA, NA, NA, NA, NA,  1,  2,  3,  4,  7,  8, NA, 8, NA };
1356 static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
1357   NA, NA, NA, NA, NA,  1, NA,  2, NA,  3,  4,  4,  4,  4 };
1358
1359
1360 /*!
1361  * This function links 2 channels together for automatic frame
1362  * synchronization. The output of the source channel is linked to the input of
1363  * the destination channel.
1364  *
1365  * @param       src_ch          Input parameter for the logical channel ID of
1366  *                              the source channel.
1367  *
1368  * @param       dest_ch         Input parameter for the logical channel ID of
1369  *                              the destination channel.
1370  *
1371  * @return      This function returns 0 on success or negative error code on
1372  *              fail.
1373  */
1374 int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
1375 {
1376         int retval = 0;
1377         unsigned long lock_flags;
1378         uint32_t fs_proc_flow1;
1379         uint32_t fs_proc_flow2;
1380         uint32_t fs_proc_flow3;
1381         uint32_t fs_disp_flow1;
1382
1383         spin_lock_irqsave(&ipu_lock, lock_flags);
1384
1385         fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
1386         fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
1387         fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
1388         fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
1389
1390         switch (src_ch) {
1391         case CSI_MEM0:
1392                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1393                 fs_proc_flow3 |=
1394                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1395                         FS_SMFC0_DEST_SEL_OFFSET;
1396                 break;
1397         case CSI_MEM1:
1398                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1399                 fs_proc_flow3 |=
1400                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1401                         FS_SMFC1_DEST_SEL_OFFSET;
1402                 break;
1403         case CSI_MEM2:
1404                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1405                 fs_proc_flow3 |=
1406                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1407                         FS_SMFC2_DEST_SEL_OFFSET;
1408                 break;
1409         case CSI_MEM3:
1410                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1411                 fs_proc_flow3 |=
1412                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1413                         FS_SMFC3_DEST_SEL_OFFSET;
1414                 break;
1415         case CSI_PRP_ENC_MEM:
1416                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1417                 fs_proc_flow2 |=
1418                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1419                         FS_PRPENC_DEST_SEL_OFFSET;
1420                 break;
1421         case CSI_PRP_VF_MEM:
1422                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1423                 fs_proc_flow2 |=
1424                         proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1425                         FS_PRPVF_DEST_SEL_OFFSET;
1426                 break;
1427         case MEM_PP_MEM:
1428                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1429                 fs_proc_flow2 |=
1430                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1431                     FS_PP_DEST_SEL_OFFSET;
1432                 break;
1433         case MEM_ROT_PP_MEM:
1434                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1435                 fs_proc_flow2 |=
1436                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1437                     FS_PP_ROT_DEST_SEL_OFFSET;
1438                 break;
1439         case MEM_PRP_ENC_MEM:
1440                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1441                 fs_proc_flow2 |=
1442                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1443                     FS_PRPENC_DEST_SEL_OFFSET;
1444                 break;
1445         case MEM_ROT_ENC_MEM:
1446                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1447                 fs_proc_flow2 |=
1448                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1449                     FS_PRPENC_ROT_DEST_SEL_OFFSET;
1450                 break;
1451         case MEM_PRP_VF_MEM:
1452                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1453                 fs_proc_flow2 |=
1454                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1455                     FS_PRPVF_DEST_SEL_OFFSET;
1456                 break;
1457         case MEM_VDI_PRP_VF_MEM:
1458                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1459                 fs_proc_flow2 |=
1460                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1461                     FS_PRPVF_DEST_SEL_OFFSET;
1462                 break;
1463         case MEM_ROT_VF_MEM:
1464                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1465                 fs_proc_flow2 |=
1466                     proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
1467                     FS_PRPVF_ROT_DEST_SEL_OFFSET;
1468                 break;
1469         default:
1470                 retval = -EINVAL;
1471                 goto err;
1472         }
1473
1474         switch (dest_ch) {
1475         case MEM_PP_MEM:
1476                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1477                 fs_proc_flow1 |=
1478                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PP_SRC_SEL_OFFSET;
1479                 break;
1480         case MEM_ROT_PP_MEM:
1481                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1482                 fs_proc_flow1 |=
1483                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1484                     FS_PP_ROT_SRC_SEL_OFFSET;
1485                 break;
1486         case MEM_PRP_ENC_MEM:
1487                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1488                 fs_proc_flow1 |=
1489                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1490                 break;
1491         case MEM_ROT_ENC_MEM:
1492                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1493                 fs_proc_flow1 |=
1494                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1495                     FS_PRPENC_ROT_SRC_SEL_OFFSET;
1496                 break;
1497         case MEM_PRP_VF_MEM:
1498                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1499                 fs_proc_flow1 |=
1500                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1501                 break;
1502         case MEM_VDI_PRP_VF_MEM:
1503                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1504                 fs_proc_flow1 |=
1505                     proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
1506                 break;
1507         case MEM_ROT_VF_MEM:
1508                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1509                 fs_proc_flow1 |=
1510                     proc_src_sel[IPU_CHAN_ID(src_ch)] <<
1511                     FS_PRPVF_ROT_SRC_SEL_OFFSET;
1512                 break;
1513         case MEM_DC_SYNC:
1514                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1515                 fs_disp_flow1 |=
1516                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
1517                 break;
1518         case MEM_BG_SYNC:
1519                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1520                 fs_disp_flow1 |=
1521                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1522                     FS_DP_SYNC0_SRC_SEL_OFFSET;
1523                 break;
1524         case MEM_FG_SYNC:
1525                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1526                 fs_disp_flow1 |=
1527                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1528                     FS_DP_SYNC1_SRC_SEL_OFFSET;
1529                 break;
1530         case MEM_DC_ASYNC:
1531                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1532                 fs_disp_flow1 |=
1533                     disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
1534                 break;
1535         case MEM_BG_ASYNC0:
1536                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1537                 fs_disp_flow1 |=
1538                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1539                     FS_DP_ASYNC0_SRC_SEL_OFFSET;
1540                 break;
1541         case MEM_FG_ASYNC0:
1542                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1543                 fs_disp_flow1 |=
1544                     disp_src_sel[IPU_CHAN_ID(src_ch)] <<
1545                     FS_DP_ASYNC1_SRC_SEL_OFFSET;
1546                 break;
1547         default:
1548                 retval = -EINVAL;
1549                 goto err;
1550         }
1551
1552         __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
1553         __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
1554         __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
1555         __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
1556
1557 err:
1558         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1559         return retval;
1560 }
1561 EXPORT_SYMBOL(ipu_link_channels);
1562
1563 /*!
1564  * This function unlinks 2 channels and disables automatic frame
1565  * synchronization.
1566  *
1567  * @param       src_ch          Input parameter for the logical channel ID of
1568  *                              the source channel.
1569  *
1570  * @param       dest_ch         Input parameter for the logical channel ID of
1571  *                              the destination channel.
1572  *
1573  * @return      This function returns 0 on success or negative error code on
1574  *              fail.
1575  */
1576 int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch)
1577 {
1578         int retval = 0;
1579         unsigned long lock_flags;
1580         uint32_t fs_proc_flow1;
1581         uint32_t fs_proc_flow2;
1582         uint32_t fs_proc_flow3;
1583         uint32_t fs_disp_flow1;
1584
1585         spin_lock_irqsave(&ipu_lock, lock_flags);
1586
1587         fs_proc_flow1 = __raw_readl(IPU_FS_PROC_FLOW1);
1588         fs_proc_flow2 = __raw_readl(IPU_FS_PROC_FLOW2);
1589         fs_proc_flow3 = __raw_readl(IPU_FS_PROC_FLOW3);
1590         fs_disp_flow1 = __raw_readl(IPU_FS_DISP_FLOW1);
1591
1592         switch (src_ch) {
1593         case CSI_MEM0:
1594                 fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
1595                 break;
1596         case CSI_MEM1:
1597                 fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
1598                 break;
1599         case CSI_MEM2:
1600                 fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
1601                 break;
1602         case CSI_MEM3:
1603                 fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
1604                 break;
1605         case CSI_PRP_ENC_MEM:
1606                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1607                 break;
1608         case CSI_PRP_VF_MEM:
1609                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1610                 break;
1611         case MEM_PP_MEM:
1612                 fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
1613                 break;
1614         case MEM_ROT_PP_MEM:
1615                 fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
1616                 break;
1617         case MEM_PRP_ENC_MEM:
1618                 fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
1619                 break;
1620         case MEM_ROT_ENC_MEM:
1621                 fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
1622                 break;
1623         case MEM_PRP_VF_MEM:
1624                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1625                 break;
1626         case MEM_VDI_PRP_VF_MEM:
1627                 fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
1628                 break;
1629         case MEM_ROT_VF_MEM:
1630                 fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
1631                 break;
1632         default:
1633                 retval = -EINVAL;
1634                 goto err;
1635         }
1636
1637         switch (dest_ch) {
1638         case MEM_PP_MEM:
1639                 fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
1640                 break;
1641         case MEM_ROT_PP_MEM:
1642                 fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
1643                 break;
1644         case MEM_PRP_ENC_MEM:
1645                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1646                 break;
1647         case MEM_ROT_ENC_MEM:
1648                 fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
1649                 break;
1650         case MEM_PRP_VF_MEM:
1651                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1652                 break;
1653         case MEM_VDI_PRP_VF_MEM:
1654                 fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
1655                 break;
1656         case MEM_ROT_VF_MEM:
1657                 fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
1658                 break;
1659         case MEM_DC_SYNC:
1660                 fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
1661                 break;
1662         case MEM_BG_SYNC:
1663                 fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
1664                 break;
1665         case MEM_FG_SYNC:
1666                 fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
1667                 break;
1668         case MEM_DC_ASYNC:
1669                 fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
1670                 break;
1671         case MEM_BG_ASYNC0:
1672                 fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
1673                 break;
1674         case MEM_FG_ASYNC0:
1675                 fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
1676                 break;
1677         default:
1678                 retval = -EINVAL;
1679                 goto err;
1680         }
1681
1682         __raw_writel(fs_proc_flow1, IPU_FS_PROC_FLOW1);
1683         __raw_writel(fs_proc_flow2, IPU_FS_PROC_FLOW2);
1684         __raw_writel(fs_proc_flow3, IPU_FS_PROC_FLOW3);
1685         __raw_writel(fs_disp_flow1, IPU_FS_DISP_FLOW1);
1686
1687 err:
1688         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1689         return retval;
1690 }
1691 EXPORT_SYMBOL(ipu_unlink_channels);
1692
1693 /*!
1694  * This function check whether a logical channel was enabled.
1695  *
1696  * @param       channel         Input parameter for the logical channel ID.
1697  *
1698  * @return      This function returns 1 while request channel is enabled or
1699  *              0 for not enabled.
1700  */
1701 int32_t ipu_is_channel_busy(ipu_channel_t channel)
1702 {
1703         uint32_t reg;
1704         uint32_t in_dma;
1705         uint32_t out_dma;
1706
1707         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1708         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1709
1710         reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1711         if (reg & idma_mask(in_dma))
1712                 return 1;
1713         reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1714         if (reg & idma_mask(out_dma))
1715                 return 1;
1716         return 0;
1717 }
1718 EXPORT_SYMBOL(ipu_is_channel_busy);
1719
1720 /*!
1721  * This function enables a logical channel.
1722  *
1723  * @param       channel         Input parameter for the logical channel ID.
1724  *
1725  * @return      This function returns 0 on success or negative error code on
1726  *              fail.
1727  */
1728 int32_t ipu_enable_channel(ipu_channel_t channel)
1729 {
1730         uint32_t reg;
1731         unsigned long lock_flags;
1732         uint32_t ipu_conf;
1733         uint32_t in_dma;
1734         uint32_t out_dma;
1735         uint32_t sec_dma;
1736         uint32_t thrd_dma;
1737
1738         spin_lock_irqsave(&ipu_lock, lock_flags);
1739
1740         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1741                 dev_err(g_ipu_dev, "Warning: channel already enabled %d\n",
1742                         IPU_CHAN_ID(channel));
1743
1744                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
1745                 return -EACCES;
1746         }
1747
1748         /* Get input and output dma channels */
1749         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1750         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1751
1752         ipu_conf = __raw_readl(IPU_CONF);
1753         if (ipu_di_use_count[0] > 0) {
1754                 ipu_conf |= IPU_CONF_DI0_EN;
1755         }
1756         if (ipu_di_use_count[1] > 0) {
1757                 ipu_conf |= IPU_CONF_DI1_EN;
1758         }
1759         if (ipu_dp_use_count > 0)
1760                 ipu_conf |= IPU_CONF_DP_EN;
1761         if (ipu_dc_use_count > 0)
1762                 ipu_conf |= IPU_CONF_DC_EN;
1763         if (ipu_dmfc_use_count > 0)
1764                 ipu_conf |= IPU_CONF_DMFC_EN;
1765         if (ipu_ic_use_count > 0)
1766                 ipu_conf |= IPU_CONF_IC_EN;
1767         if (ipu_vdi_use_count > 0) {
1768                 ipu_conf |= IPU_CONF_ISP_EN;
1769                 ipu_conf |= IPU_CONF_VDI_EN;
1770                 ipu_conf |= IPU_CONF_IC_INPUT;
1771         }
1772         if (ipu_rot_use_count > 0)
1773                 ipu_conf |= IPU_CONF_ROT_EN;
1774         if (ipu_smfc_use_count > 0)
1775                 ipu_conf |= IPU_CONF_SMFC_EN;
1776         __raw_writel(ipu_conf, IPU_CONF);
1777
1778         if (idma_is_valid(in_dma)) {
1779                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1780                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1781         }
1782         if (idma_is_valid(out_dma)) {
1783                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1784                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1785         }
1786
1787         if ((g_sec_chan_en[IPU_CHAN_ID(channel)]) &&
1788                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
1789                  (channel == MEM_VDI_PRP_VF_MEM))) {
1790                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1791                 reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
1792                 __raw_writel(reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
1793         }
1794         if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1795                 ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
1796                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1797                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
1798                 __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
1799
1800                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1801                 reg = __raw_readl(IDMAC_SEP_ALPHA);
1802                 __raw_writel(reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
1803         } else if ((g_thrd_chan_en[IPU_CHAN_ID(channel)]) &&
1804                    ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
1805                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1806                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
1807                 __raw_writel(reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
1808                 reg = __raw_readl(IDMAC_SEP_ALPHA);
1809                 __raw_writel(reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
1810         }
1811
1812         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1813             (channel == MEM_FG_SYNC)) {
1814                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
1815                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
1816
1817                 _ipu_dp_dc_enable(channel);
1818         }
1819
1820         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
1821                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
1822                 _ipu_ic_enable_task(channel);
1823
1824         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1825
1826         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1827
1828         return 0;
1829 }
1830 EXPORT_SYMBOL(ipu_enable_channel);
1831
1832 /*!
1833  * This function check buffer ready for a logical channel.
1834  *
1835  * @param       channel         Input parameter for the logical channel ID.
1836  *
1837  * @param       type            Input parameter which buffer to clear.
1838  *
1839  * @param       bufNum          Input parameter for which buffer number clear
1840  *                              ready state.
1841  *
1842  */
1843 int32_t ipu_check_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1844                 uint32_t bufNum)
1845 {
1846         uint32_t dma_chan = channel_2_dma(channel, type);
1847         uint32_t reg;
1848
1849         if (dma_chan == IDMA_CHAN_INVALID)
1850                 return -EINVAL;
1851
1852         if (bufNum == 0)
1853                 reg = __raw_readl(IPU_CHA_BUF0_RDY(dma_chan));
1854         else if (bufNum == 1)
1855                 reg = __raw_readl(IPU_CHA_BUF1_RDY(dma_chan));
1856         else
1857                 reg = __raw_readl(IPU_CHA_BUF2_RDY(dma_chan));
1858
1859         if (reg & idma_mask(dma_chan))
1860                 return 1;
1861         else
1862                 return 0;
1863 }
1864 EXPORT_SYMBOL(ipu_check_buffer_ready);
1865
1866 /*!
1867  * This function clear buffer ready for a logical channel.
1868  *
1869  * @param       channel         Input parameter for the logical channel ID.
1870  *
1871  * @param       type            Input parameter which buffer to clear.
1872  *
1873  * @param       bufNum          Input parameter for which buffer number clear
1874  *                              ready state.
1875  *
1876  */
1877 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1878                 uint32_t bufNum)
1879 {
1880         unsigned long lock_flags;
1881         uint32_t dma_ch = channel_2_dma(channel, type);
1882
1883         if (!idma_is_valid(dma_ch))
1884                 return;
1885
1886         spin_lock_irqsave(&ipu_lock, lock_flags);
1887         __raw_writel(0xF0300000, IPU_GPR); /* write one to clear */
1888         if (bufNum == 0) {
1889                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1890                         __raw_writel(idma_mask(dma_ch),
1891                                         IPU_CHA_BUF0_RDY(dma_ch));
1892                 }
1893         } else if (bufNum == 1) {
1894                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1895                         __raw_writel(idma_mask(dma_ch),
1896                                         IPU_CHA_BUF1_RDY(dma_ch));
1897                 }
1898         } else {
1899                 if (idma_is_set(IPU_CHA_BUF2_RDY, dma_ch)) {
1900                         __raw_writel(idma_mask(dma_ch),
1901                                         IPU_CHA_BUF2_RDY(dma_ch));
1902                 }
1903         }
1904         __raw_writel(0x0, IPU_GPR); /* write one to set */
1905         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1906 }
1907 EXPORT_SYMBOL(ipu_clear_buffer_ready);
1908
1909 void _ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1910                              uint32_t bufNum)
1911 {
1912         uint32_t dma_ch = channel_2_dma(channel, type);
1913
1914         if (!idma_is_valid(dma_ch))
1915                 return;
1916
1917         __raw_writel(0xF0300000, IPU_GPR); /* write one to clear */
1918         if (bufNum == 0) {
1919                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1920                         __raw_writel(idma_mask(dma_ch),
1921                                         IPU_CHA_BUF0_RDY(dma_ch));
1922                 }
1923         } else if (bufNum == 1) {
1924                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1925                         __raw_writel(idma_mask(dma_ch),
1926                                         IPU_CHA_BUF1_RDY(dma_ch));
1927                 }
1928         } else {
1929                 if (idma_is_set(IPU_CHA_BUF2_RDY, dma_ch)) {
1930                         __raw_writel(idma_mask(dma_ch),
1931                                         IPU_CHA_BUF2_RDY(dma_ch));
1932                 }
1933         }
1934         __raw_writel(0x0, IPU_GPR); /* write one to set */
1935 }
1936
1937 static irqreturn_t disable_chan_irq_handler(int irq, void *dev_id)
1938 {
1939         struct completion *comp = dev_id;
1940
1941         complete(comp);
1942         return IRQ_HANDLED;
1943 }
1944
1945 /*!
1946  * This function disables a logical channel.
1947  *
1948  * @param       channel         Input parameter for the logical channel ID.
1949  *
1950  * @param       wait_for_stop   Flag to set whether to wait for channel end
1951  *                              of frame or return immediately.
1952  *
1953  * @return      This function returns 0 on success or negative error code on
1954  *              fail.
1955  */
1956 int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop)
1957 {
1958         uint32_t reg;
1959         unsigned long lock_flags;
1960         uint32_t in_dma;
1961         uint32_t out_dma;
1962         uint32_t sec_dma = NO_DMA;
1963         uint32_t thrd_dma = NO_DMA;
1964
1965         spin_lock_irqsave(&ipu_lock, lock_flags);
1966
1967         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1968                 dev_info(g_ipu_dev, "Channel already disabled %d\n",
1969                         IPU_CHAN_ID(channel));
1970
1971                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
1972                 return -EACCES;
1973         }
1974
1975         spin_unlock_irqrestore(&ipu_lock, lock_flags);
1976
1977         /* Get input and output dma channels */
1978         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1979         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1980
1981         if ((idma_is_valid(in_dma) &&
1982                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1983                 && (idma_is_valid(out_dma) &&
1984                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1985                 return -EINVAL;
1986
1987         if (g_sec_chan_en[IPU_CHAN_ID(channel)])
1988                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1989         if (g_thrd_chan_en[IPU_CHAN_ID(channel)]) {
1990                 sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
1991                 thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
1992         }
1993
1994         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1995             (channel == MEM_DC_SYNC)) {
1996                 if (channel == MEM_FG_SYNC)
1997                         ipu_disp_set_window_pos(channel, 0, 0);
1998
1999                 _ipu_dp_dc_disable(channel, false);
2000
2001                 /*
2002                  * wait for BG channel EOF then disable FG-IDMAC,
2003                  * it avoid FG NFB4EOF error.
2004                  */
2005                 if (channel == MEM_FG_SYNC) {
2006                         int timeout = 50;
2007
2008                         __raw_writel(IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
2009                                         IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
2010                         while ((__raw_readl(IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
2011                                         IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
2012                                 msleep(10);
2013                                 timeout -= 10;
2014                                 if (timeout <= 0) {
2015                                         dev_err(g_ipu_dev, "warning: wait for bg sync eof timeout\n");
2016                                         break;
2017                                 }
2018                         }
2019                 }
2020         } else if (wait_for_stop) {
2021                 while (idma_is_set(IDMAC_CHA_BUSY, in_dma) ||
2022                        idma_is_set(IDMAC_CHA_BUSY, out_dma) ||
2023                         (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
2024                         idma_is_set(IDMAC_CHA_BUSY, sec_dma)) ||
2025                         (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
2026                         idma_is_set(IDMAC_CHA_BUSY, thrd_dma))) {
2027                         uint32_t ret, irq = 0xffffffff;
2028                         DECLARE_COMPLETION_ONSTACK(disable_comp);
2029
2030                         if (idma_is_set(IDMAC_CHA_BUSY, out_dma))
2031                                 irq = out_dma;
2032                         if (g_sec_chan_en[IPU_CHAN_ID(channel)] &&
2033                                 idma_is_set(IDMAC_CHA_BUSY, sec_dma))
2034                                 irq = sec_dma;
2035                         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] &&
2036                                 idma_is_set(IDMAC_CHA_BUSY, thrd_dma))
2037                                 irq = thrd_dma;
2038                         if (idma_is_set(IDMAC_CHA_BUSY, in_dma))
2039                                 irq = in_dma;
2040
2041                         if (irq == 0xffffffff) {
2042                                 dev_err(g_ipu_dev, "warning: no channel busy, break\n");
2043                                 break;
2044                         }
2045                         ret = ipu_request_irq(irq, disable_chan_irq_handler, 0, NULL, &disable_comp);
2046                         if (ret < 0) {
2047                                 dev_err(g_ipu_dev, "irq %d in use\n", irq);
2048                                 break;
2049                         } else {
2050                                 ret = wait_for_completion_timeout(&disable_comp, msecs_to_jiffies(200));
2051                                 ipu_free_irq(irq, &disable_comp);
2052                                 if (ret == 0) {
2053                                         ipu_dump_registers();
2054                                         dev_err(g_ipu_dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
2055                                         break;
2056                                 }
2057                         }
2058                 }
2059         }
2060
2061         spin_lock_irqsave(&ipu_lock, lock_flags);
2062
2063         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
2064             (channel == MEM_DC_SYNC)) {
2065                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
2066                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
2067         }
2068
2069         /* Disable IC task */
2070         if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
2071                 _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma))
2072                 _ipu_ic_disable_task(channel);
2073
2074         /* Disable DMA channel(s) */
2075         if (idma_is_valid(in_dma)) {
2076                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
2077                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
2078                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
2079                 __raw_writel(tri_cur_buf_mask(in_dma),
2080                                         IPU_CHA_TRIPLE_CUR_BUF(in_dma));
2081         }
2082         if (idma_is_valid(out_dma)) {
2083                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
2084                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
2085                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
2086                 __raw_writel(tri_cur_buf_mask(out_dma),
2087                                         IPU_CHA_TRIPLE_CUR_BUF(out_dma));
2088         }
2089         if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2090                 reg = __raw_readl(IDMAC_CHA_EN(sec_dma));
2091                 __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
2092                 __raw_writel(idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
2093         }
2094         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2095                 reg = __raw_readl(IDMAC_CHA_EN(thrd_dma));
2096                 __raw_writel(reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
2097                 if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
2098                         reg = __raw_readl(IDMAC_SEP_ALPHA);
2099                         __raw_writel(reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
2100                 } else {
2101                         reg = __raw_readl(IDMAC_SEP_ALPHA);
2102                         __raw_writel(reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
2103                 }
2104                 __raw_writel(idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
2105         }
2106
2107         /* Set channel buffers NOT to be ready */
2108         if (idma_is_valid(in_dma)) {
2109                 _ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
2110                 _ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
2111                 _ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 2);
2112         }
2113         if (idma_is_valid(out_dma)) {
2114                 _ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
2115                 _ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
2116         }
2117         if (g_sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
2118                 _ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 0);
2119                 _ipu_clear_buffer_ready(channel, IPU_GRAPH_IN_BUFFER, 1);
2120         }
2121         if (g_thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
2122                 _ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 0);
2123                 _ipu_clear_buffer_ready(channel, IPU_ALPHA_IN_BUFFER, 1);
2124         }
2125
2126         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
2127
2128         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2129
2130         return 0;
2131 }
2132 EXPORT_SYMBOL(ipu_disable_channel);
2133
2134 /*!
2135  * This function enables CSI.
2136  *
2137  * @param       csi     csi num 0 or 1
2138  *
2139  * @return      This function returns 0 on success or negative error code on
2140  *              fail.
2141  */
2142 int32_t ipu_enable_csi(uint32_t csi)
2143 {
2144         uint32_t reg;
2145         unsigned long lock_flags;
2146
2147         if (csi > 1) {
2148                 dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
2149                 return -EINVAL;
2150         }
2151
2152         spin_lock_irqsave(&ipu_lock, lock_flags);
2153         ipu_csi_use_count[csi]++;
2154
2155         if (ipu_csi_use_count[csi] == 1) {
2156                 reg = __raw_readl(IPU_CONF);
2157                 if (csi == 0)
2158                         __raw_writel(reg | IPU_CONF_CSI0_EN, IPU_CONF);
2159                 else
2160                         __raw_writel(reg | IPU_CONF_CSI1_EN, IPU_CONF);
2161         }
2162         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2163         return 0;
2164 }
2165 EXPORT_SYMBOL(ipu_enable_csi);
2166
2167 /*!
2168  * This function disables CSI.
2169  *
2170  * @param       csi     csi num 0 or 1
2171  *
2172  * @return      This function returns 0 on success or negative error code on
2173  *              fail.
2174  */
2175 int32_t ipu_disable_csi(uint32_t csi)
2176 {
2177         uint32_t reg;
2178         unsigned long lock_flags;
2179
2180         if (csi > 1) {
2181                 dev_err(g_ipu_dev, "Wrong csi num_%d\n", csi);
2182                 return -EINVAL;
2183         }
2184
2185         spin_lock_irqsave(&ipu_lock, lock_flags);
2186         ipu_csi_use_count[csi]--;
2187
2188         if (ipu_csi_use_count[csi] == 0) {
2189                 reg = __raw_readl(IPU_CONF);
2190                 if (csi == 0)
2191                         __raw_writel(reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
2192                 else
2193                         __raw_writel(reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
2194         }
2195         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2196         return 0;
2197 }
2198 EXPORT_SYMBOL(ipu_disable_csi);
2199
2200 static irqreturn_t ipu_irq_handler(int irq, void *desc)
2201 {
2202         int i;
2203         uint32_t line;
2204         irqreturn_t result = IRQ_NONE;
2205         uint32_t int_stat;
2206         const int err_reg[] = { 5, 6, 9, 10, 0 };
2207         const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
2208
2209         for (i = 0;; i++) {
2210                 if (err_reg[i] == 0)
2211                         break;
2212                 int_stat = __raw_readl(IPU_INT_STAT(err_reg[i]));
2213                 int_stat &= __raw_readl(IPU_INT_CTRL(err_reg[i]));
2214                 if (int_stat) {
2215                         __raw_writel(int_stat, IPU_INT_STAT(err_reg[i]));
2216                         dev_err(g_ipu_dev,
2217                                 "IPU Error - IPU_INT_STAT_%d = 0x%08X\n",
2218                                 err_reg[i], int_stat);
2219                         /* Disable interrupts so we only get error once */
2220                         int_stat =
2221                             __raw_readl(IPU_INT_CTRL(err_reg[i])) & ~int_stat;
2222                         __raw_writel(int_stat, IPU_INT_CTRL(err_reg[i]));
2223                 }
2224         }
2225
2226         for (i = 0;; i++) {
2227                 if (int_reg[i] == 0)
2228                         break;
2229                 int_stat = __raw_readl(IPU_INT_STAT(int_reg[i]));
2230                 int_stat &= __raw_readl(IPU_INT_CTRL(int_reg[i]));
2231                 __raw_writel(int_stat, IPU_INT_STAT(int_reg[i]));
2232                 while ((line = ffs(int_stat)) != 0) {
2233                         line--;
2234                         int_stat &= ~(1UL << line);
2235                         line += (int_reg[i] - 1) * 32;
2236                         result |=
2237                             ipu_irq_list[line].handler(line,
2238                                                        ipu_irq_list[line].
2239                                                        dev_id);
2240                 }
2241         }
2242
2243         return result;
2244 }
2245
2246 /*!
2247  * This function enables the interrupt for the specified interrupt line.
2248  * The interrupt lines are defined in \b ipu_irq_line enum.
2249  *
2250  * @param       irq             Interrupt line to enable interrupt for.
2251  *
2252  */
2253 void ipu_enable_irq(uint32_t irq)
2254 {
2255         uint32_t reg;
2256         unsigned long lock_flags;
2257
2258         if (!g_ipu_clk_enabled)
2259                 clk_enable(g_ipu_clk);
2260
2261         spin_lock_irqsave(&ipu_lock, lock_flags);
2262
2263         reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
2264         reg |= IPUIRQ_2_MASK(irq);
2265         __raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
2266
2267         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2268         if (!g_ipu_clk_enabled)
2269                 clk_disable(g_ipu_clk);
2270 }
2271 EXPORT_SYMBOL(ipu_enable_irq);
2272
2273 /*!
2274  * This function disables the interrupt for the specified interrupt line.
2275  * The interrupt lines are defined in \b ipu_irq_line enum.
2276  *
2277  * @param       irq             Interrupt line to disable interrupt for.
2278  *
2279  */
2280 void ipu_disable_irq(uint32_t irq)
2281 {
2282         uint32_t reg;
2283         unsigned long lock_flags;
2284
2285         if (!g_ipu_clk_enabled)
2286                 clk_enable(g_ipu_clk);
2287         spin_lock_irqsave(&ipu_lock, lock_flags);
2288
2289         reg = __raw_readl(IPUIRQ_2_CTRLREG(irq));
2290         reg &= ~IPUIRQ_2_MASK(irq);
2291         __raw_writel(reg, IPUIRQ_2_CTRLREG(irq));
2292
2293         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2294         if (!g_ipu_clk_enabled)
2295                 clk_disable(g_ipu_clk);
2296 }
2297 EXPORT_SYMBOL(ipu_disable_irq);
2298
2299 /*!
2300  * This function clears the interrupt for the specified interrupt line.
2301  * The interrupt lines are defined in \b ipu_irq_line enum.
2302  *
2303  * @param       irq             Interrupt line to clear interrupt for.
2304  *
2305  */
2306 void ipu_clear_irq(uint32_t irq)
2307 {
2308         if (!g_ipu_clk_enabled)
2309                 clk_enable(g_ipu_clk);
2310
2311         __raw_writel(IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
2312
2313         if (!g_ipu_clk_enabled)
2314                 clk_disable(g_ipu_clk);
2315 }
2316 EXPORT_SYMBOL(ipu_clear_irq);
2317
2318 /*!
2319  * This function returns the current interrupt status for the specified
2320  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2321  *
2322  * @param       irq             Interrupt line to get status for.
2323  *
2324  * @return      Returns true if the interrupt is pending/asserted or false if
2325  *              the interrupt is not pending.
2326  */
2327 bool ipu_get_irq_status(uint32_t irq)
2328 {
2329         uint32_t reg;
2330
2331         if (!g_ipu_clk_enabled)
2332                 clk_enable(g_ipu_clk);
2333
2334         reg = __raw_readl(IPUIRQ_2_STATREG(irq));
2335
2336         if (!g_ipu_clk_enabled)
2337                 clk_disable(g_ipu_clk);
2338
2339         if (reg & IPUIRQ_2_MASK(irq))
2340                 return true;
2341         else
2342                 return false;
2343 }
2344 EXPORT_SYMBOL(ipu_get_irq_status);
2345
2346 /*!
2347  * This function registers an interrupt handler function for the specified
2348  * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
2349  *
2350  * @param       irq             Interrupt line to get status for.
2351  *
2352  * @param       handler         Input parameter for address of the handler
2353  *                              function.
2354  *
2355  * @param       irq_flags       Flags for interrupt mode. Currently not used.
2356  *
2357  * @param       devname         Input parameter for string name of driver
2358  *                              registering the handler.
2359  *
2360  * @param       dev_id          Input parameter for pointer of data to be
2361  *                              passed to the handler.
2362  *
2363  * @return      This function returns 0 on success or negative error code on
2364  *              fail.
2365  */
2366 int ipu_request_irq(uint32_t irq,
2367                     irqreturn_t(*handler) (int, void *),
2368                     uint32_t irq_flags, const char *devname, void *dev_id)
2369 {
2370         unsigned long lock_flags;
2371
2372         BUG_ON(irq >= IPU_IRQ_COUNT);
2373
2374         spin_lock_irqsave(&ipu_lock, lock_flags);
2375
2376         if (ipu_irq_list[irq].handler != NULL) {
2377                 dev_err(g_ipu_dev,
2378                         "handler already installed on irq %d\n", irq);
2379                 spin_unlock_irqrestore(&ipu_lock, lock_flags);
2380                 return -EINVAL;
2381         }
2382
2383         ipu_irq_list[irq].handler = handler;
2384         ipu_irq_list[irq].flags = irq_flags;
2385         ipu_irq_list[irq].dev_id = dev_id;
2386         ipu_irq_list[irq].name = devname;
2387
2388         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2389
2390         ipu_enable_irq(irq);    /* enable the interrupt */
2391
2392         return 0;
2393 }
2394 EXPORT_SYMBOL(ipu_request_irq);
2395
2396 /*!
2397  * This function unregisters an interrupt handler for the specified interrupt
2398  * line. The interrupt lines are defined in \b ipu_irq_line enum.
2399  *
2400  * @param       irq             Interrupt line to get status for.
2401  *
2402  * @param       dev_id          Input parameter for pointer of data to be passed
2403  *                              to the handler. This must match value passed to
2404  *                              ipu_request_irq().
2405  *
2406  */
2407 void ipu_free_irq(uint32_t irq, void *dev_id)
2408 {
2409         ipu_disable_irq(irq);   /* disable the interrupt */
2410
2411         if (ipu_irq_list[irq].dev_id == dev_id)
2412                 ipu_irq_list[irq].handler = NULL;
2413 }
2414 EXPORT_SYMBOL(ipu_free_irq);
2415
2416 uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type)
2417 {
2418         uint32_t reg, dma_chan;
2419
2420         dma_chan = channel_2_dma(channel, type);
2421         if (!idma_is_valid(dma_chan))
2422                 return -EINVAL;
2423
2424         reg = __raw_readl(IPU_CHA_TRB_MODE_SEL(dma_chan));
2425         if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
2426                 reg = __raw_readl(IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
2427                 return (reg & tri_cur_buf_mask(dma_chan)) >>
2428                                 tri_cur_buf_shift(dma_chan);
2429         } else {
2430                 reg = __raw_readl(IPU_CHA_CUR_BUF(dma_chan));
2431                 if (reg & idma_mask(dma_chan))
2432                         return 1;
2433                 else
2434                         return 0;
2435         }
2436 }
2437 EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
2438
2439 uint32_t _ipu_channel_status(ipu_channel_t channel)
2440 {
2441         uint32_t stat = 0;
2442         uint32_t task_stat_reg = __raw_readl(IPU_PROC_TASK_STAT);
2443
2444         switch (channel) {
2445         case MEM_PRP_VF_MEM:
2446                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2447                 break;
2448         case MEM_VDI_PRP_VF_MEM:
2449                 stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
2450                 break;
2451         case MEM_ROT_VF_MEM:
2452                 stat =
2453                     (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
2454                 break;
2455         case MEM_PRP_ENC_MEM:
2456                 stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
2457                 break;
2458         case MEM_ROT_ENC_MEM:
2459                 stat =
2460                     (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
2461                     TSTAT_ENC_ROT_OFFSET;
2462                 break;
2463         case MEM_PP_MEM:
2464                 stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
2465                 break;
2466         case MEM_ROT_PP_MEM:
2467                 stat =
2468                     (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
2469                 break;
2470
2471         default:
2472                 stat = TASK_STAT_IDLE;
2473                 break;
2474         }
2475         return stat;
2476 }
2477
2478 int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch)
2479 {
2480         uint32_t reg;
2481         unsigned long lock_flags;
2482
2483         int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
2484         int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
2485
2486         /* enable target channel */
2487         spin_lock_irqsave(&ipu_lock, lock_flags);
2488
2489         reg = __raw_readl(IDMAC_CHA_EN(to_dma));
2490         __raw_writel(reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
2491
2492         g_channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
2493
2494         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2495
2496         /* switch dp dc */
2497         _ipu_dp_dc_disable(from_ch, true);
2498
2499         /* disable source channel */
2500         spin_lock_irqsave(&ipu_lock, lock_flags);
2501
2502         reg = __raw_readl(IDMAC_CHA_EN(from_dma));
2503         __raw_writel(reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
2504         __raw_writel(idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
2505         __raw_writel(tri_cur_buf_mask(from_dma),
2506                                 IPU_CHA_TRIPLE_CUR_BUF(from_dma));
2507
2508         _ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 0);
2509         _ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 1);
2510         _ipu_clear_buffer_ready(from_ch, IPU_VIDEO_IN_BUFFER, 2);
2511
2512         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
2513
2514         spin_unlock_irqrestore(&ipu_lock, lock_flags);
2515
2516         return 0;
2517 }
2518 EXPORT_SYMBOL(ipu_swap_channel);
2519
2520 uint32_t bytes_per_pixel(uint32_t fmt)
2521 {
2522         switch (fmt) {
2523         case IPU_PIX_FMT_GENERIC:       /*generic data */
2524         case IPU_PIX_FMT_RGB332:
2525         case IPU_PIX_FMT_YUV420P:
2526         case IPU_PIX_FMT_YVU420P:
2527         case IPU_PIX_FMT_YUV422P:
2528                 return 1;
2529                 break;
2530         case IPU_PIX_FMT_RGB565:
2531         case IPU_PIX_FMT_YUYV:
2532         case IPU_PIX_FMT_UYVY:
2533                 return 2;
2534                 break;
2535         case IPU_PIX_FMT_BGR24:
2536         case IPU_PIX_FMT_RGB24:
2537                 return 3;
2538                 break;
2539         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
2540         case IPU_PIX_FMT_BGR32:
2541         case IPU_PIX_FMT_BGRA32:
2542         case IPU_PIX_FMT_RGB32:
2543         case IPU_PIX_FMT_RGBA32:
2544         case IPU_PIX_FMT_ABGR32:
2545                 return 4;
2546                 break;
2547         default:
2548                 return 1;
2549                 break;
2550         }
2551         return 0;
2552 }
2553 EXPORT_SYMBOL(bytes_per_pixel);
2554
2555 ipu_color_space_t format_to_colorspace(uint32_t fmt)
2556 {
2557         switch (fmt) {
2558         case IPU_PIX_FMT_RGB666:
2559         case IPU_PIX_FMT_RGB565:
2560         case IPU_PIX_FMT_BGR24:
2561         case IPU_PIX_FMT_RGB24:
2562         case IPU_PIX_FMT_GBR24:
2563         case IPU_PIX_FMT_BGR32:
2564         case IPU_PIX_FMT_BGRA32:
2565         case IPU_PIX_FMT_RGB32:
2566         case IPU_PIX_FMT_RGBA32:
2567         case IPU_PIX_FMT_ABGR32:
2568         case IPU_PIX_FMT_LVDS666:
2569         case IPU_PIX_FMT_LVDS888:
2570                 return RGB;
2571                 break;
2572
2573         default:
2574                 return YCbCr;
2575                 break;
2576         }
2577         return RGB;
2578 }
2579
2580 bool ipu_pixel_format_has_alpha(uint32_t fmt)
2581 {
2582         switch (fmt) {
2583         case IPU_PIX_FMT_RGBA32:
2584         case IPU_PIX_FMT_BGRA32:
2585         case IPU_PIX_FMT_ABGR32:
2586                 return true;
2587                 break;
2588         default:
2589                 return false;
2590                 break;
2591         }
2592         return false;
2593 }
2594
2595 void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3])
2596 {
2597         _ipu_dp_set_csc_coefficients(channel, param);
2598 }
2599 EXPORT_SYMBOL(ipu_set_csc_coefficients);
2600
2601 static int ipu_suspend(struct platform_device *pdev, pm_message_t state)
2602 {
2603         if (g_ipu_clk_enabled) {
2604                 uint32_t chan_should_disable, timeout = 1000, time = 0;
2605
2606                 /* save and disable enabled channels*/
2607                 idma_enable_reg[0] = __raw_readl(IDMAC_CHA_EN(0));
2608                 idma_enable_reg[1] = __raw_readl(IDMAC_CHA_EN(32));
2609                 while ((__raw_readl(IDMAC_CHA_BUSY(0)) & idma_enable_reg[0])
2610                         || (__raw_readl(IDMAC_CHA_BUSY(32)) &
2611                                 idma_enable_reg[1])) {
2612                         /* disable channel not busy already */
2613                         chan_should_disable =
2614                                 __raw_readl(IDMAC_CHA_BUSY(0))
2615                                         ^ idma_enable_reg[0];
2616                         __raw_writel((~chan_should_disable) &
2617                                         idma_enable_reg[0], IDMAC_CHA_EN(0));
2618                         chan_should_disable =
2619                                 __raw_readl(IDMAC_CHA_BUSY(1))
2620                                         ^ idma_enable_reg[1];
2621                         __raw_writel((~chan_should_disable) &
2622                                         idma_enable_reg[1], IDMAC_CHA_EN(32));
2623                         msleep(2);
2624