7 years agoENGR00125056-1 MX50: add one wire pin configuration
Frank Li [Mon, 12 Jul 2010 08:17:51 +0000 (16:17 +0800)]
ENGR00125056-1 MX50: add one wire pin configuration

Add "w1" setup at mx50 pin defination because 1wire pin used
for usb over current default.
Fix multi w1_setup problem at many i.MX platform. Only first one
is run by main.

Signed-off-by: Frank Li <Frank.Li@freescale.com>
7 years agoENGR00125251 usb_gadget: should not read PORT Reset at reset_irq
Peter Chen [Fri, 16 Jul 2010 12:28:05 +0000 (20:28 +0800)]
ENGR00125251 usb_gadget: should not read PORT Reset at reset_irq

1. At reset_irq, the status of port reset is unsure, maybe the reset
process(hardware does it) is finished, and the status of port reset
is also cleared by usb controller. So it only needs to compare to USBSTS
at usb irq process.

2. Due to mx35/mx25 phy's bug, it needs to reset phy when re-open
usb clock next time(Begin to use usb next time)

3. mdelay 100 seconds is too long for resume process, as this code
is only added for mx37, add arch macro for this mdelay. This can
minimize the effect for other platforms.

4. Compile is ok for all imx platform, functional tests are finished
for mx35 and mx23.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
7 years agoENGR00125052-3 Enable the eMMC44 DDR mode on MX53 EVK
Richard Zhu [Tue, 13 Jul 2010 03:07:26 +0000 (11:07 +0800)]
ENGR00125052-3 Enable the eMMC44 DDR mode on MX53 EVK

The platform related codes' modifications
when enable the eMMC44 DDR mode on MX53 EVK board

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00125052-2 Driver modifications when enable the eMMC44 DDR
Richard Zhu [Tue, 13 Jul 2010 03:06:30 +0000 (11:06 +0800)]
ENGR00125052-2 Driver modifications when enable the eMMC44 DDR

The driver related codes' modifications
when enable the eMMC44 DDR mode on MX53 EVK board

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00125052-1 Common codes changes when enable the eMMC44 DDR
Richard Zhu [Mon, 12 Jul 2010 09:31:44 +0000 (17:31 +0800)]
ENGR00125052-1 Common codes changes when enable the eMMC44 DDR

The modifications of linux kernel common codes
when enable the eMMC44 DDR mode

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00125206 mmc: update clock setting for mx50
Aisheng.Dong [Thu, 15 Jul 2010 11:17:50 +0000 (19:17 +0800)]
ENGR00125206 mmc: update clock setting for mx50

The clock prescaler can not be 0 for esdhc v3 in MX50.
(The smallest value should be 1).
Change the clock setting part to cover this special case.

Signed-off-by: Aisheng.Dong <b29396@freescale.com>
7 years agoENGR00125205 mx50: add esdhc3 support
Aisheng.Dong [Tue, 13 Jul 2010 08:50:17 +0000 (16:50 +0800)]
ENGR00125205 mx50: add esdhc3 support

Add IOMUX and configuration data for esdhc3

Signed-off-by: Aisheng.Dong <b29396@freescale.com>
7 years agoENGR00124989-3 ELCDIF:Support ELCDIF framebuffer driver
Liu Ying [Tue, 13 Jul 2010 09:39:46 +0000 (17:39 +0800)]
ENGR00124989-3 ELCDIF:Support ELCDIF framebuffer driver

1) Support ELCDIF framebuffer driver.
2) Change CLAA WVGA LCD driver to make it co-work with ELCDIF driver.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124989-2 MX5:Change CLAA-WVGA LCD panel video mode
Liu Ying [Tue, 13 Jul 2010 09:38:55 +0000 (17:38 +0800)]
ENGR00124989-2 MX5:Change CLAA-WVGA LCD panel video mode

Set pixel clock rate for CLAA-WVGA LCD panel for 27MHz and
set the display frequency to be 57Hz. This makes the panel
to get rid of water wave glitch issue on MX50 platform.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124989-1 MX508:Configure ELCDIF pads attribute
Liu Ying [Tue, 13 Jul 2010 09:38:07 +0000 (17:38 +0800)]
ENGR00124989-1 MX508:Configure ELCDIF pads attribute

1) Enable keepers for LCDIF pads.
2) Remove input path selection for LCDIF pads.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124132 MX53: busfreq driver support
Shen Yong [Mon, 28 Jun 2010 05:14:22 +0000 (13:14 +0800)]
ENGR00124132 MX53: busfreq driver support

1. adjust lp_clk, ddr_clk MX53 and MX51 uses different one
2. adjust cpu rate in cpu_wp_table
3. enable clock divider handshaking when ddr clock changing
4. add AHB_MED_SET_POINT to ldb_di_clk
5. adjust the bit define about CCDR register

Signed-off-by: Shen Yong <b00984@freescale.com>
7 years agoENGR00125010-3 MX35: add gpu to imx35_3stack_defconfig
Richard Zhao [Wed, 14 Jul 2010 06:02:36 +0000 (14:02 +0800)]
ENGR00125010-3 MX35: add gpu to imx35_3stack_defconfig

Build as module by default.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
7 years agoENGR00125010-2 MX5: add gpu to imx5_defconfig
Richard Zhao [Wed, 14 Jul 2010 05:57:48 +0000 (13:57 +0800)]
ENGR00125010-2 MX5: add gpu to imx5_defconfig

Build as module by default.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
7 years agoENGR00125010-1 gpu: add gpu driver support
Gene Chouiniere [Tue, 29 Jun 2010 09:20:51 +0000 (17:20 +0800)]
ENGR00125010-1 gpu: add gpu driver support

Migrate from RC14 with freescale changes.

Signed-off-by: Gene Chouiniere <Gene.Chouiniere@amd.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Rob Herring <r.herring@freescale.com>
7 years agoENGR00125173 ipuv3: remove stat check wait in _ipu_dp_dc_disable()
Jason Chen [Thu, 15 Jul 2010 03:19:08 +0000 (11:19 +0800)]
ENGR00125173 ipuv3: remove stat check wait in _ipu_dp_dc_disable()

The stat check wait will add ipu operation time which degrade the ipu

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00125172 ipuv3 fb: add sync for DP swap
Jason Chen [Thu, 15 Jul 2010 03:08:46 +0000 (11:08 +0800)]
ENGR00125172 ipuv3 fb: add sync for DP swap

During DP swap, other fb operation should not happen.

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00125171 ipu dev: add sync method
Jason Chen [Thu, 15 Jul 2010 03:02:24 +0000 (11:02 +0800)]
ENGR00125171 ipu dev: add sync method

The memory mmap by ipu device is write-back, so user space need sync

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00125045 MX53: Adjust VDDGP voltage setting
Lily Zhang [Tue, 13 Jul 2010 07:24:18 +0000 (15:24 +0800)]
ENGR00125045 MX53: Adjust VDDGP voltage setting

1. Adjust VDDGP for 1GHZ as 1.15v
2. Adjust VDDGP for 800MHZ as 1.05v
3. Not all current MX53 boards can run up to 1GHZ. So one limitation is
added into clock.c to limit 1GHZ working point. To enable 1GHZ
working point in kernel, please increase the GP voltage and type the
command "clk core 1000" in uboot console to switch CPU core to 1GHZ.
This limitation will be removed after all boards support 1GHZ.

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoENGR00125169 MX5: only reset nfc in arch_reset when we have it
Richard Zhao [Thu, 15 Jul 2010 02:57:14 +0000 (10:57 +0800)]
ENGR00125169 MX5: only reset nfc in arch_reset when we have it

it fix mx50 reboot wdog reg write failed issue.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
7 years agoENGR00125175 Add pxp_dma.h into include/linux/KBuild
Robby Cai [Thu, 15 Jul 2010 04:53:32 +0000 (12:53 +0800)]
ENGR00125175 Add pxp_dma.h into include/linux/KBuild

Add pxp_dma.h into KBuild

Signed-off-by: Robby Cai <R63905@freescale.com>
7 years agoENGR00125120 - EPDC fb: Hangs when display pmic regulators not found
Danny Nold [Wed, 14 Jul 2010 01:20:05 +0000 (20:20 -0500)]
ENGR00125120 - EPDC fb: Hangs when display pmic regulators not found

EPDC driver updated to fail gracefully when the display pmic cannot
be acquired.  No longer hanging.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00125119 - Maxim 17135 display pmic: VCOM configured incorrectly
Danny Nold [Wed, 14 Jul 2010 00:57:10 +0000 (19:57 -0500)]
ENGR00125119 - Maxim 17135 display pmic: VCOM configured incorrectly

The initial VCOM voltage should be configured once.  Previously it was
left unconfigured.  Now, the VCOM value is checked the first time
through, and if it is not set correctly, it will be fixed.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00125118 - Maxim 17135 display pmic: increase PWR_GOOD wait timeout
Danny Nold [Tue, 13 Jul 2010 18:52:17 +0000 (13:52 -0500)]
ENGR00125118 - Maxim 17135 display pmic: increase PWR_GOOD wait timeout

A number of Maxim 17135 parts were found to require longer than the
computed max wait time to assert the PWR_GOOD signal, indicating that
display power is up and valid.  This fix increases the timeout,
preventing regulator_enable calls from prematurely bailing out
and reporting errors.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00125113 - imx5_defconfig update - Add PxP, Max17135, and EPDC
Danny Nold [Tue, 13 Jul 2010 14:16:51 +0000 (09:16 -0500)]
ENGR00125113 - imx5_defconfig update - Add PxP, Max17135, and EPDC

MX50 requires inclusion of PxP, Maxim 17135, and EPDC drivers as defaults
in order to have proper E-Ink display support.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00125077: pmic battery: disable battery for MX50 Arm2 board
Zhou Jingyu [Tue, 13 Jul 2010 03:28:20 +0000 (11:28 +0800)]
ENGR00125077: pmic battery: disable battery for MX50 Arm2 board

pmic battery: disable battery for MX50 Arm2 board

Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
7 years agoENGR00124255 Reconfigure MX5x's eSDHC iomux PAD's configurations
Richard Zhu [Mon, 12 Jul 2010 07:29:24 +0000 (15:29 +0800)]
ENGR00124255 Reconfigure MX5x's eSDHC iomux PAD's configurations

Reconfigure the PAD's configurations to level up the HW
timing compatibility.

MX51:Some MMC cards such as transcend mmc plus cards can't
be recognized and initialized correctly on the second
esdhc slot of the BBG boards that populated the new DDR chips.
MX53:Same Kingstone SDHC card can work well on EVK REVA board, but
failed in initialization on EVK REVB board without
any sw modifications.
After adjust the slot pin's pad configurations,
fix the HW compatible issues listed above.

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00124814-2 firmware: add e-ink panel waveform
Danny Nold [Sat, 3 Jul 2010 05:16:09 +0000 (00:16 -0500)]
ENGR00124814-2 firmware: add e-ink panel waveform

Added default E-Ink panel waveform.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00124814-1 fb: Add i.MX EPDC fb driver
Danny Nold [Fri, 9 Jul 2010 16:07:11 +0000 (11:07 -0500)]
ENGR00124814-1 fb: Add i.MX EPDC fb driver

Added basic EPDC driver, including support for PXP conversions (rotation,
auto-waveform selection, CSC).  Self-clock gating also supported.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00125034 [MX50] Add PxP DMA-Engine and PxP client driver
Robby Cai [Fri, 9 Jul 2010 22:37:42 +0000 (06:37 +0800)]
ENGR00125034 [MX50] Add PxP DMA-Engine and PxP client driver

Use Common DMA-Engine framework to implement ePXP driver
Use a dma client driver to access ePxP staff.

Signed-off-by: Danny Nold <dannynold@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
7 years agoENGR00124812-2: MX50 add Max17135 Display pmic init to MSL
Danny Nold [Mon, 12 Jul 2010 20:25:27 +0000 (15:25 -0500)]
ENGR00124812-2: MX50 add Max17135 Display pmic init to MSL

Maxim 17135 PMIC init added to MSL in conjunction with addition
of Maxim 17135 regulator driver and I2C client.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00124812-1: Support Maxim E-Ink PMIC
Danny Nold [Mon, 12 Jul 2010 20:23:21 +0000 (15:23 -0500)]
ENGR00124812-1: Support Maxim E-Ink PMIC

Added new regulator driver to control voltage supplies for
E-Ink panel.

Signed-off-by: Danny Nold <dannynold@freescale.com>
7 years agoENGR00124942 MX51: YUV422 output for 720P data
mark gutman [Wed, 7 Jul 2010 14:13:09 +0000 (17:13 +0300)]
ENGR00124942 MX51: YUV422 output for 720P data

Ignore UGDE using for non YUYV output formats

Signed-off-by: Mark Gutman <r58412@freescale.com>
7 years agoENGR00124963 USB: add vbus enable/disable
Hu hui [Mon, 12 Jul 2010 01:54:08 +0000 (09:54 +0800)]
ENGR00124963 USB: add vbus enable/disable

support imx53 evk board OTG and Host1 vbus active
and inactive to low the power consume, fix fsl_otg.c
build failt, add vbus power control function pointer
in struct fsl_usb2_platform_data.

Signed-off-by: Hu hui <b29976@freescale.com>
7 years agoENGR00125007: MX50: Correct PAD settings for over-current detection
Dinh Nguyen [Fri, 9 Jul 2010 16:00:32 +0000 (11:00 -0500)]
ENGR00125007: MX50: Correct PAD settings for over-current detection

The pad settings for the over-current detection pins on MX50 ARM2
CPU board needs to have a pull-up.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
7 years agoENGR00124986 mx5: add gpu refcounting and increase command buffer
Rob Herring [Fri, 13 Nov 2009 20:04:25 +0000 (14:04 -0600)]
ENGR00124986 mx5: add gpu refcounting and increase command buffer

Add reference counting of driver opens for multi-context support.
Increase command buffer to 64KB.

Signed-off-by: Rob Herring <r.herring@freescale.com>
7 years agoENGR00125012: fix cspi mater driver clock polarity for cpsi v7
Zhou Jingyu [Fri, 9 Jul 2010 09:20:49 +0000 (17:20 +0800)]
ENGR00125012:  fix cspi mater driver clock polarity for cpsi v7

fix cspi mater driver clock polarity for cpsi v7

Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
7 years agoENGR00124956 Increase vpu iram size to 80K
Sammy He [Fri, 9 Jul 2010 15:48:36 +0000 (23:48 +0800)]
ENGR00124956 Increase vpu iram size to 80K

Increase vpu iram size to 80K on mx51 and mx53 to
use more iram for video decoding and encoding.
It can cover 720P encoder and 1080P decoder except VC-1 AP.

Signed-off-by: Sammy He <r62914@freescale.com>w
7 years agoENGR00124905 rtc: remove MX51 1.0 work-around
Anish Trivedi [Tue, 6 Jul 2010 19:58:14 +0000 (14:58 -0500)]
ENGR00124905 rtc: remove MX51 1.0 work-around

Since some chips don't have IIM, remove work-around

Signed-off-by: Anish Trivedi <anish@freescale.com>
7 years agoENGR00124849-3 mx5: add mx50 support
Rob Herring [Wed, 7 Jul 2010 22:51:47 +0000 (17:51 -0500)]
ENGR00124849-3 mx5: add mx50 support

Add support for i.MX50 and arm2 board with lpddr/mddr.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Rob Herring <r.herring@freescale.com>
7 years agoENGR00124849-2: mx5: clean-up serial configuration code
Rob Herring [Thu, 8 Jul 2010 16:39:39 +0000 (11:39 -0500)]
ENGR00124849-2: mx5: clean-up serial configuration code

The serial device setup code includes board configuration header,
but is common for all boards. So make the configuration common for
all boards and remove the board headers as nothing else is used.

Signed-off-by: Rob Herring <r.herring@freescale.com>
7 years agoENGR00124849-1 mx5: clean-up some includes of crm_regs.h
Rob Herring [Wed, 7 Jul 2010 20:41:41 +0000 (15:41 -0500)]
ENGR00124849-1 mx5: clean-up some includes of crm_regs.h

CCM is different on various MX5x chips, so limit its include.
SRPG is only initialized on MX51 3DS, but should be done on all
MX5x chips.

Signed-off-by: Rob Herring <r.herring@freescale.com>
7 years agoENGR00124740-4 MX25/35 ALSA: Changes due to ESAI as platform device
William Lai [Thu, 1 Jul 2010 01:36:48 +0000 (09:36 +0800)]
ENGR00124740-4 MX25/35 ALSA: Changes due to ESAI as platform device

Make ESAI as a platform device, and pass the audio data to use
the external memory by default.

Signed-off-by: William Lai <b04597@freescale.com>
7 years agoENGR00124740-3 MX53 : Multi-channel audio support
William Lai [Wed, 30 Jun 2010 11:37:15 +0000 (19:37 +0800)]
ENGR00124740-3 MX53 : Multi-channel audio support

CS4288 is built in as default for MX53, but with a command parameter
of apc in the commandline to enable.

Signed-off-by: William Lai <b04597@freescale.com>
7 years agoENGR00124740-2 ALSA: CS42888 codec driver support
William Lai [Mon, 5 Jul 2010 08:37:22 +0000 (16:37 +0800)]
ENGR00124740-2 ALSA: CS42888 codec driver support

Support CS42888 playback and recording.
ESAI_HCKT is used to drive CS42888 when recording, due to
hardware layout.

Signed-off-by: William Lai <b04597@freescale.com>
7 years agoENGR00124740-1 MX53 ALSA: Make ESAI as a platform device
William Lai [Mon, 5 Jul 2010 07:55:18 +0000 (15:55 +0800)]
ENGR00124740-1 MX53 ALSA: Make ESAI as a platform device

Make ESAI a platform device and pass the register base address
by resource and then use ioremap.

Signed-off-by: William Lai <b04597@freescale.com>
7 years agoENGR00124955 sgtl5000: fix audio power down pop
Alan Tull [Wed, 7 Jul 2010 17:49:56 +0000 (12:49 -0500)]
ENGR00124955 sgtl5000: fix audio power down pop

Some boards need a longer delay after powering off VAG.

Signed-off-by: Alan Tull <r80115@freescale.com>
7 years agoRevert "ENGR00124852 sgtl5000: support nonstandard sample rates"
Alan Tull [Wed, 7 Jul 2010 18:57:01 +0000 (13:57 -0500)]
Revert "ENGR00124852 sgtl5000: support nonstandard sample rates"

This reverts commit 33391f8b0a2ccda3a27d95dfe67846d5c60666f7.

Signed-off-by: Alan Tull <r80115@freescale.com>
7 years agoENGR00124831 USB-UDC: Delete the useless code
Peter Chen [Fri, 2 Jul 2010 07:27:29 +0000 (15:27 +0800)]
ENGR00124831 USB-UDC: Delete the useless code

The probe is called only pdev->name is the same with driver_name,
So the statement for name judgement is useless.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
7 years agoENGR00124761 V4L2 still:Support to capture QXGA still image
Liu Ying [Wed, 30 Jun 2010 05:32:01 +0000 (13:32 +0800)]
ENGR00124761 V4L2 still:Support to capture QXGA still image

1) Add OV3640 camera QXGA configuration at 7.5fps support.
2) Use double buffer to workaround tearing issue when capturing
   still image.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124256 Linux platform integrated AHCI SATA driver
Richard Zhu [Tue, 6 Jul 2010 03:33:48 +0000 (11:33 +0800)]
ENGR00124256 Linux platform integrated AHCI SATA driver

Sata can work well on EVK boards, and pass the unit-tests.

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00124864 MX5: Fix MSL issue
Lily Zhang [Mon, 5 Jul 2010 12:42:10 +0000 (20:42 +0800)]
ENGR00124864 MX5: Fix MSL issue

1. correct mx53 sdma script variable
2. CSPI should not use cspi_main_clk
3. remove duplicated M4IF setting codes in clock.c, which
are already in cpu.c

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoENGR00124736 Remerge the minor modifications to mainline
Richard Zhu [Tue, 29 Jun 2010 07:07:56 +0000 (15:07 +0800)]
ENGR00124736 Remerge the minor modifications to mainline

1 correct the pata platform device resource check codes
2 Change the end statment of the sdhc1 det pin
iomux definition on mx51 board from ',' to ';'.
3 sdhc driver max blk count on MX31, sinc
customer report that the emmc would be failed when
the blk count is more than 32.

Signed-off-by: Richard Zhu <r65037@freescale.com>
7 years agoENGR00124828 v4l2 output: close overlay for ic bypass mode
Jason Chen [Mon, 5 Jul 2010 06:40:21 +0000 (14:40 +0800)]
ENGR00124828 v4l2 output: close overlay for ic bypass mode

After streamoff, ic bypass mode should close overlay like others

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00124827 ipuv3 fb: long time jitter issue
Jason Chen [Mon, 5 Jul 2010 05:53:26 +0000 (13:53 +0800)]
ENGR00124827 ipuv3 fb: long time jitter issue

Call pan display frequently(for example display through ipu lib),
sometime it will jitter.

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00124795 SPI NOR: uniform include header file
Lily Zhang [Thu, 1 Jul 2010 06:55:38 +0000 (14:55 +0800)]
ENGR00124795 SPI NOR: uniform include header file

The default partitions are missing in MX53 SPI NOR MTD.
It's because spi nor driver and mx53 msl include different
header files. It causes struct definitions are different.
For i.MX SPI nor driver, need to use asm/mach/flash.h by
aligning with NAND driver.

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoENGR00124852 sgtl5000: support nonstandard sample rates
Alan Tull [Fri, 2 Jul 2010 13:29:19 +0000 (08:29 -0500)]
ENGR00124852 sgtl5000: support nonstandard sample rates

Supporting more sample rates that are not listed in pcm.h
(12KHz and 24KHz).

Signed-off-by: Alan Tull <r80115@freescale.com>
7 years agoENGR00124760 fec: set mac address correctly
Jason Chen [Wed, 30 Jun 2010 03:25:26 +0000 (11:25 +0800)]
ENGR00124760 fec: set mac address correctly

Fix dynamicly set mac address make network hang issue.

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00124629 mx5x: Add Watchdog config for mfg defconfig
Peter Chen [Thu, 24 Jun 2010 07:47:42 +0000 (15:47 +0800)]
ENGR00124629 mx5x: Add Watchdog config for mfg defconfig

If not, the board will be reset as no one
serices the watchdog.
At USB recovery mode, the watchdog will be
enabled at rom code.

Signed-off-by: Peter Chen <b29397@freescale.com>
7 years agoENGR00124762 MX5: Fix clock div zero issue
Lily Zhang [Wed, 30 Jun 2010 05:05:08 +0000 (13:05 +0800)]
ENGR00124762 MX5: Fix clock div zero issue

Fix clock div zero issue in mx5 clock file

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoENGR00124683-3 Add ADV7180 TV decoder support on mx53
Sammy He [Tue, 29 Jun 2010 15:56:36 +0000 (23:56 +0800)]
ENGR00124683-3 Add ADV7180 TV decoder support on mx53

Add ADV7180 TV decoder support on mx53. OV3640 module must be
removed before ADV7180 TVIN test.

Signed-off-by: Sammy He <r62914@freescale.com>
7 years agoENGR00124683-2 Change adv7180_pwdn callback function on mx35
Sammy He [Fri, 25 Jun 2010 16:25:42 +0000 (00:25 +0800)]
ENGR00124683-2 Change adv7180_pwdn callback function on mx35

Change adv7180_pwdn callback function on mx35 due to pwdn parameter
defintion update.

Signed-off-by: Sammy He <r62914@freescale.com>
7 years agoENGR00124683-1 Add CCIR interlaced mode for TV decoder
Sammy He [Fri, 25 Jun 2010 15:59:08 +0000 (23:59 +0800)]
ENGR00124683-1 Add CCIR interlaced mode for TV decoder

Add CCIR interlaced mode for TV decoder. And add pwdn callback
function in mxc_camera_platform_data.

Signed-off-by: Sammy He <r62914@freescale.com>
7 years agoENGR00124719 ipuv3 fb: pan display for special format
Jason Chen [Tue, 29 Jun 2010 03:28:55 +0000 (11:28 +0800)]
ENGR00124719 ipuv3 fb: pan display for special format

If set fb's fmt to I420, pan display will get wrong result.

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00124653 ipuv3 fb: pan display issue
Jason Chen [Fri, 25 Jun 2010 03:33:57 +0000 (11:33 +0800)]
ENGR00124653 ipuv3 fb: pan display issue

Call pan display frequently, after a long time, it has chance to show
below error msg:

Error updating SDC buf ....

check buffer busy before update buffer function call to avoid such

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00124569 IPUv3:Change for support VDI in IPU lib
Liu Ying [Fri, 25 Jun 2010 17:55:49 +0000 (13:55 -0400)]
ENGR00124569 IPUv3:Change for support VDI in IPU lib

1) Support select VDI input channel buffer ioctrl.
2) Add VDI input channels' EOF interrupt.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124082-2 V4L2 output:Rework VDI V4L2 output implementation
Liu Ying [Fri, 25 Jun 2010 17:17:26 +0000 (13:17 -0400)]
ENGR00124082-2 V4L2 output:Rework VDI V4L2 output implementation

1)Medium motion and low motion:
  Frame(n)'s even field is used for Previous channel,
  Frame(n+1)'s odd field is used for Current channel and
  Frame(n+1)'s even field is used for Next channel to generate
  de-interlaced Frame(n+1).
2)High motion:
  Frame(n)'s odd field is used for Current channel to generate
  de-interlaced Frame(n).

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124082-1 IPUv3:Fix some bugs related with VDI
Liu Ying [Fri, 25 Jun 2010 17:16:27 +0000 (13:16 -0400)]
ENGR00124082-1 IPUv3:Fix some bugs related with VDI

1) Read buffer 1 ready register before setting buffer 1 ready.
2) Enable ISP in IPU_CONF when using VDI.
3) Fix link issue between MEM_VDI_PRP_VF_MEM and MEM_ROT_VF_MEM.
4) Correct g_channel_init_mask value.
5) Use fixed top field for VDI.

Signed-off-by: Liu Ying <b17645@freescale.com>
7 years agoENGR00124252 MX28: Support Switch port0 as ethernet port
Niu Xule [Wed, 9 Jun 2010 06:40:23 +0000 (14:40 +0800)]
ENGR00124252 MX28: Support Switch port0 as ethernet port

The L2 Switch have 4 ports,
and the port0 can be used as ethernet port
when Switch is configured to operate
as a 3-Port Switch (Switch Mode).

Signed-off-by: Niu Xule <b23300@freescale.com>
7 years agoENGR00124085 MX23 ALSA: To reduce the start/stop/pause pop noise when playback
Lionel Xu [Wed, 2 Jun 2010 05:19:20 +0000 (13:19 +0800)]
ENGR00124085 MX23 ALSA: To reduce the start/stop/pause pop noise when playback

1)There is still pop noise sometimes when start/stop/pausing a playback,
   this patch is used to further reduce the pop noise.
2)Enter low power mode(power down DAC) when there is no playback for 5 seconds.
3)Modify amixer controls "Speaker Playback Switch" and "Headhpone Playback

Signed-off-by: Lionel Xu <r63889@freescale.com>
7 years agoENGR00122302 MX23 ALSA: Resolve the failure when pausing and resuming playback
Lionel Xu [Tue, 18 May 2010 07:31:20 +0000 (15:31 +0800)]
ENGR00122302 MX23 ALSA: Resolve the failure when pausing and resuming playback

To reslove the problem when resuming a playback from pausing

Signed-off-by: Lionel Xu <r63889@freescale.com>
7 years agoENGR00124360 v4l2 output: rework v4l2 output
Jason Chen [Thu, 24 Jun 2010 01:39:40 +0000 (09:39 +0800)]
ENGR00124360 v4l2 output: rework v4l2 output

1. remove ADC support.
2. remove work queue for not ic bypass mode which improve the

Signed-off-by: Jason Chen <b02280@freescale.com>
7 years agoENGR00123738 MX53: Fix MLB issue caused by emi_int2 clock
Lily Zhang [Mon, 21 Jun 2010 03:21:23 +0000 (11:21 +0800)]
ENGR00123738 MX53: Fix MLB issue caused by emi_int2 clock

1. MLB can only work with "jtag=on" option enable or after system
resume now. It's cuased by emi_int2 clock gate bit setting.
MX53 enables the internal memory power saving mode which requires
emi_intr CCGR bits must be set as 0x11 if using IRAM. To fix current
issue, add additional mlb clock which is associated with emi_int2.
2. Update MLB PIN setting.

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoENGR00124562 MX28 add persistent bit support
Frank Li [Tue, 22 Jun 2010 01:55:47 +0000 (09:55 +0800)]
ENGR00124562 MX28 add persistent bit support

Add persistent bit for MX28

Signed-off-by: Frank Li <Frank.Li@freescale.com>
7 years agoENGR00124477 MXC-Nand: Add disable BI swap entry at sys filesystem
Peter Chen [Thu, 17 Jun 2010 08:57:58 +0000 (16:57 +0800)]
ENGR00124477 MXC-Nand: Add disable BI swap entry at sys filesystem

In that case, the user can choose not to swap BI
if necessary, such as programming the bootloader.

Signed-off-by: Peter Chen <b29397@freescale.com>
7 years agoENGR00124390 MX35:Update new mfg defconfig for supporting both sd and nand
Peter Chen [Thu, 17 Jun 2010 03:03:02 +0000 (11:03 +0800)]
ENGR00124390 MX35:Update new mfg defconfig for supporting both sd and nand

The old one can't work and no ubi support

Signed-off-by: Peter Chen <b29397@freescale.com>
7 years agoENGR00119736 MX51: YUV422 output for 720P data
mark gutman [Tue, 8 Jun 2010 12:38:58 +0000 (15:38 +0300)]
ENGR00119736 MX51: YUV422 output for 720P data

The support for YUV422 different combinations are added
The YUV422 is supported for DI1 interface for 720P frames with 16bits bus  only:
di1_primary video=mxcdi1fb:YUYV16,720P60
To define required YUV422 format use one of:

Signed-off-by: Mark Gutman <r58412@freescale.com>
7 years agoENGR00124287 MX5x, MX37: Fix DVFS memory resource issue
Nancy Chen [Wed, 9 Jun 2010 18:49:47 +0000 (13:49 -0500)]
ENGR00124287 MX5x, MX37: Fix DVFS memory resource issue

MX5x, MX37: Fix DVFS memory resource issue.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>
7 years agoENGR00124326 MX53: Add SPDIF Tx support
Lily Zhang [Fri, 11 Jun 2010 01:47:28 +0000 (09:47 +0800)]
ENGR00124326 MX53: Add SPDIF Tx support

Add SPDIF Tx support for MX53 EVK board.
1. Support 44.1KHZ sample rate.
2. 48K and 32K sample rates require 24.576MHZ OSC connected to
CKIH2. But it's "DNP" in EVK.

Test conditions:
1. Connect MX51 Accessory Card with J94 port in EVK.
2. SPDIF_OUT pin conflicts with 12V pin used by CAN feature.
Add "spdif" command option in the command line to enable SPDIF

Signed-off-by: Lily Zhang <r58066@freescale.com>
7 years agoahci: Add platform driver
Anton Vorontsov [Thu, 4 Mar 2010 17:06:06 +0000 (20:06 +0300)]
ahci: Add platform driver

This can be used for AHCI-compatible interfaces implemented inside
System-On-Chip solutions, or AHCI devices connected via localbus.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Move generic code into libahci
Anton Vorontsov [Sun, 28 Mar 2010 04:22:14 +0000 (00:22 -0400)]
ahci: Move generic code into libahci

This patch should contain no functional changes, just moves code

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Introduce ahci_set_em_messages()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:45 +0000 (20:17 +0300)]
ahci: Introduce ahci_set_em_messages()

Factor out some ahci_em_messages handling code from ahci_init_one().
We would like to reuse it for non-PCI devices.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Factor out PCI specifics from ahci_print_info()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:43 +0000 (20:17 +0300)]
ahci: Factor out PCI specifics from ahci_print_info()

Introduce ahci_pci_print_info() that now handles PCI stuff.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Factor out PCI specifics from ahci_init_controller()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:42 +0000 (20:17 +0300)]
ahci: Factor out PCI specifics from ahci_init_controller()

Move PCI stuff into ahci_pci_init_controller().

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Get rid of pci_dev argument in ahci_port_init()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:40 +0000 (20:17 +0300)]
ahci: Get rid of pci_dev argument in ahci_port_init()

To make the function bus-independand we have to get rid of
"struct pci_dev *", so let's pass just "struct devce *".

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Factor out PCI specifics from ahci_reset_controller()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:39 +0000 (20:17 +0300)]
ahci: Factor out PCI specifics from ahci_reset_controller()

Move PCI stuff into ahci_pci_reset_controller().

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Get rid of pci_dev argument in ahci_save_initial_config()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:37 +0000 (20:17 +0300)]
ahci: Get rid of pci_dev argument in ahci_save_initial_config()

To make the function generic we have to get rid of "struct pci_dev *",
so let's pass just a "struct devce *".

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Factor out PCI specifics from ahci_save_initial_config()
Anton Vorontsov [Wed, 3 Mar 2010 17:17:36 +0000 (20:17 +0300)]
ahci: Factor out PCI specifics from ahci_save_initial_config()

Make ahci_save_initial_config() a bit more generic by introducing
force_port_map and mask_port_map arguments.

Move PCI stuff into ahci_pci_save_initial_config().

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Get rid of host->iomap usage
Anton Vorontsov [Wed, 3 Mar 2010 17:17:34 +0000 (20:17 +0300)]
ahci: Get rid of host->iomap usage

Currently the driver uses host->iomap to store all the iomapped BARs
of a PCI device (while AHCI devices actually use just a single memory

We're going to teach AHCI to work with non-PCI buses, so there are two
options to make this work:

1. "fake" host->iomap array for non-PCI devices, and place the needed
   address at iomap[AHCI_PCI_BAR];
2. Get rid of host->iomap usage, instead introduce a private mmio

This patch implements the second option.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: pp->active_link is not reliable when FBS is enabled
Shane Huang [Tue, 16 Mar 2010 10:08:55 +0000 (18:08 +0800)]
ahci: pp->active_link is not reliable when FBS is enabled

pp->active_link is not reliable when FBS is enabled.
Both PORT_SCR_ACT and PORT_CMD_ISSUE should be checked
because mixed NCQ and non-NCQ commands may be in flight.

Signed-off-by: Shane Huang <shane.huang@amd.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agolibata: make functions/variables static
Robert Hancock [Wed, 20 Jan 2010 05:03:39 +0000 (23:03 -0600)]
libata: make functions/variables static

Make some variables in ahci and a function in pata_pcmcia static, as found
using sparse.

Signed-off-by: Robert Hancock <hancockrwd@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Implement SATA AHCI FIS-based switching support
Shane Huang [Wed, 9 Dec 2009 09:23:04 +0000 (17:23 +0800)]
ahci: Implement SATA AHCI FIS-based switching support

Tested on AMD internal reference board.

Signed-off-by: Shane Huang <shane.huang@amd.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: disable SNotification capability for ich8
Shaohua Li [Mon, 16 Nov 2009 01:56:05 +0000 (09:56 +0800)]
ahci: disable SNotification capability for ich8

I obseved there is a sata_async_notification() for every ahci
interrupt. But the async notification does nothing (this is hard
disk drive and no pmp). This cause cpu wastes some time on sntf
register access.

It appears ICH AHCI doesn't support SNotification register, but the
controller reports it does. After quirking it, the async notification

PS. it appears all ICH don't support SNotification register from ICH
manual, don't know if we need quirk all ICH. I don't have machines
with all kinds of ICH.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: Add ifdef wrapper to ahci_gtf_filter_workaround
Markus Trippelsdorf [Fri, 9 Oct 2009 03:41:47 +0000 (05:41 +0200)]
ahci: Add ifdef wrapper to ahci_gtf_filter_workaround

Commit f80ae7e45a0e03da188494c6e947a5c8b0cdfb4a
ahci: filter FPDMA non-zero offset enable for Aspire 3810T
breaks the current git build for configurations that don't define
This adds an ifdef wrapper to ahci_gtf_filter_workaround.

Signed-off-by: Markus Trippelsdorf <markus@trippelsdorf.de>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: filter FPDMA non-zero offset enable for Aspire 3810T
Tejun Heo [Tue, 15 Sep 2009 19:18:03 +0000 (04:18 +0900)]
ahci: filter FPDMA non-zero offset enable for Aspire 3810T

Curiously, Aspire 3810T issues many SATA feature enable commands via
_GTF, of which one is invalid and another is not supported by the
drive.  In the process, it also enables FPDMA non-zero offset.
However, the feature also needs to be supported and enabled from the
controller and it's wrong to enable it from _GTF unless the controller
can do it by default.

Currently, this ends up enabling FPDMA non-zero offset only on the
drive side leading to NCQ command failures and eventual disabling of
NCQ.  This patch makes libata filter out FPDMA non-zero offset enable
for the machine.

This was reported by Marcus Meissner in bnc#522790.


Reported-by: Marcus Meissner <meissner@novell.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: display all AHCI 1.3 HBA capability flags (v2)
Robert Hancock [Sun, 20 Sep 2009 23:02:31 +0000 (17:02 -0600)]
ahci: display all AHCI 1.3 HBA capability flags (v2)

Update the AHCI driver to display all of the HBA capabilities defined in the
AHCI 1.3 specification. Some of these are in a new CAP2 (HBA Capabilities
Extended) register which is only defined on AHCI 1.2 or later. The spec says
that undefined registers should always return 0 on read, but to be safe we
assume a value of 0 unless the controller reports AHCI version 1.2 or later.
The value can also be retrieved through sysfs as with the existing capability

For example, on an Intel Ibex Peak (PCH) controller:

ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pmp pio slum part ems
sxs apst

We don't do anything special with the new flags yet.

Also, change the code that displays the flags to use the same bit enumerations
that are used to control actual operation.

Signed-off-by: Robert Hancock <hancockrwd@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoahci: kill @force_restart and refine CLO for ahci_kick_engine()
Shane Huang [Fri, 7 Aug 2009 07:05:52 +0000 (15:05 +0800)]
ahci: kill @force_restart and refine CLO for ahci_kick_engine()

This patch refines ahci_kick_engine() after discussion with Tejun about
FBS(FIS-based switching) support preparation:
a. Kill @force_restart and always kick the engine. The only case where
   @force_restart is zero is when it's called from ahci_p5wdh_hardreset()
   Actually at that point, BSY is pretty much guaranteed to be set.
b. If PMP is attached, ignore busy and always do CLO. (AHCI-1.3 9.2)

Signed-off-by: Shane Huang <shane.huang@amd.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agolibata: Export AHCI capabilities
Matthew Garrett [Fri, 17 Jul 2009 18:13:47 +0000 (19:13 +0100)]
libata: Export AHCI capabilities

AHCI exports various capability bits that may be of interest to userspace
such as whether the BIOS claims a port is hotpluggable or eSATA. Providing
these via sysfs along with the version of the AHCI spec implemented by
the host allows userspace to make policy decisions for things like ALPM.

Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years ago[libata] add DMA setup FIS auto-activate feature
Shaohua Li [Mon, 27 Jul 2009 01:24:35 +0000 (09:24 +0800)]
[libata] add DMA setup FIS auto-activate feature

Hopefully results in fewer on-the-wire FIS's and no breakage.  We'll see!

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
7 years agoENGR00124224 mx51: Update the new mfg default config according to mx5_defconfig
Peter Chen [Tue, 8 Jun 2010 12:07:01 +0000 (20:07 +0800)]
ENGR00124224 mx51: Update the new mfg default config according to mx5_defconfig

The old imx51_updater_defconfig is out-dated, so delete it,
and mfg firmware will use imx5_updater_defconfig in future.

Signed-off-by: Peter Chen <b29397@freescale.com>
7 years agoENGR00120301 MX51: Fix slow TS issue
Nancy Chen [Mon, 7 Jun 2010 15:45:08 +0000 (10:45 -0500)]
ENGR00120301 MX51: Fix slow TS issue

MX51: Fix slow TS issue.

Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com>