Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[efikamx:linux-kernel.git] / drivers / pci / setup-bus.c
1 /*
2  *      drivers/pci/setup-bus.c
3  *
4  * Extruded from code written by
5  *      Dave Rusling (david.rusling@reo.mts.dec.com)
6  *      David Mosberger (davidm@cs.arizona.edu)
7  *      David Miller (davem@redhat.com)
8  *
9  * Support routines for initializing a PCI subsystem.
10  */
11
12 /*
13  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14  *           PCI-PCI bridges cleanup, sorted resource allocation.
15  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16  *           Converted to allocation in 3 passes, which gives
17  *           tighter packing. Prefetchable range support.
18  */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28
29
30 static void pbus_assign_resources_sorted(const struct pci_bus *bus)
31 {
32         struct pci_dev *dev;
33         struct resource *res;
34         struct resource_list head, *list, *tmp;
35         int idx;
36
37         head.next = NULL;
38         list_for_each_entry(dev, &bus->devices, bus_list) {
39                 u16 class = dev->class >> 8;
40
41                 /* Don't touch classless devices or host bridges or ioapics.  */
42                 if (class == PCI_CLASS_NOT_DEFINED ||
43                     class == PCI_CLASS_BRIDGE_HOST)
44                         continue;
45
46                 /* Don't touch ioapic devices already enabled by firmware */
47                 if (class == PCI_CLASS_SYSTEM_PIC) {
48                         u16 command;
49                         pci_read_config_word(dev, PCI_COMMAND, &command);
50                         if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
51                                 continue;
52                 }
53
54                 pdev_sort_resources(dev, &head);
55         }
56
57         for (list = head.next; list;) {
58                 res = list->res;
59                 idx = res - &list->dev->resource[0];
60                 if (pci_assign_resource(list->dev, idx)) {
61                         /* FIXME: get rid of this */
62                         res->start = 0;
63                         res->end = 0;
64                         res->flags = 0;
65                 }
66                 tmp = list;
67                 list = list->next;
68                 kfree(tmp);
69         }
70 }
71
72 void pci_setup_cardbus(struct pci_bus *bus)
73 {
74         struct pci_dev *bridge = bus->self;
75         struct pci_bus_region region;
76
77         dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
78                  pci_domain_nr(bus), bus->number);
79
80         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
81         if (bus->resource[0]->flags & IORESOURCE_IO) {
82                 /*
83                  * The IO resource is allocated a range twice as large as it
84                  * would normally need.  This allows us to set both IO regs.
85                  */
86                 dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
87                        (unsigned long)region.start,
88                        (unsigned long)region.end);
89                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
90                                         region.start);
91                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
92                                         region.end);
93         }
94
95         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
96         if (bus->resource[1]->flags & IORESOURCE_IO) {
97                 dev_info(&bridge->dev, "  IO window: %#08lx-%#08lx\n",
98                        (unsigned long)region.start,
99                        (unsigned long)region.end);
100                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
101                                         region.start);
102                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
103                                         region.end);
104         }
105
106         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
107         if (bus->resource[2]->flags & IORESOURCE_MEM) {
108                 dev_info(&bridge->dev, "  PREFETCH window: %#08lx-%#08lx\n",
109                        (unsigned long)region.start,
110                        (unsigned long)region.end);
111                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
112                                         region.start);
113                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
114                                         region.end);
115         }
116
117         pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
118         if (bus->resource[3]->flags & IORESOURCE_MEM) {
119                 dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
120                        (unsigned long)region.start,
121                        (unsigned long)region.end);
122                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
123                                         region.start);
124                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
125                                         region.end);
126         }
127 }
128 EXPORT_SYMBOL(pci_setup_cardbus);
129
130 /* Initialize bridges with base/limit values we have collected.
131    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
132    requires that if there is no I/O ports or memory behind the
133    bridge, corresponding range must be turned off by writing base
134    value greater than limit to the bridge's base/limit registers.
135
136    Note: care must be taken when updating I/O base/limit registers
137    of bridges which support 32-bit I/O. This update requires two
138    config space writes, so it's quite possible that an I/O window of
139    the bridge will have some undesirable address (e.g. 0) after the
140    first write. Ditto 64-bit prefetchable MMIO.  */
141 static void pci_setup_bridge(struct pci_bus *bus)
142 {
143         struct pci_dev *bridge = bus->self;
144         struct pci_bus_region region;
145         u32 l, bu, lu, io_upper16;
146
147         if (pci_is_enabled(bridge))
148                 return;
149
150         dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
151                  pci_domain_nr(bus), bus->number);
152
153         /* Set up the top and bottom of the PCI I/O segment for this bus. */
154         pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
155         if (bus->resource[0]->flags & IORESOURCE_IO) {
156                 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
157                 l &= 0xffff0000;
158                 l |= (region.start >> 8) & 0x00f0;
159                 l |= region.end & 0xf000;
160                 /* Set up upper 16 bits of I/O base/limit. */
161                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
162                 dev_info(&bridge->dev, "  IO window: %#04lx-%#04lx\n",
163                     (unsigned long)region.start,
164                     (unsigned long)region.end);
165         }
166         else {
167                 /* Clear upper 16 bits of I/O base/limit. */
168                 io_upper16 = 0;
169                 l = 0x00f0;
170                 dev_info(&bridge->dev, "  IO window: disabled\n");
171         }
172         /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
173         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
174         /* Update lower 16 bits of I/O base/limit. */
175         pci_write_config_dword(bridge, PCI_IO_BASE, l);
176         /* Update upper 16 bits of I/O base/limit. */
177         pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
178
179         /* Set up the top and bottom of the PCI Memory segment
180            for this bus. */
181         pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
182         if (bus->resource[1]->flags & IORESOURCE_MEM) {
183                 l = (region.start >> 16) & 0xfff0;
184                 l |= region.end & 0xfff00000;
185                 dev_info(&bridge->dev, "  MEM window: %#08lx-%#08lx\n",
186                     (unsigned long)region.start,
187                     (unsigned long)region.end);
188         }
189         else {
190                 l = 0x0000fff0;
191                 dev_info(&bridge->dev, "  MEM window: disabled\n");
192         }
193         pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
194
195         /* Clear out the upper 32 bits of PREF limit.
196            If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
197            disables PREF range, which is ok. */
198         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
199
200         /* Set up PREF base/limit. */
201         bu = lu = 0;
202         pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
203         if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
204                 l = (region.start >> 16) & 0xfff0;
205                 l |= region.end & 0xfff00000;
206                 bu = upper_32_bits(region.start);
207                 lu = upper_32_bits(region.end);
208                 dev_info(&bridge->dev, "  PREFETCH window: %#016llx-%#016llx\n",
209                     (unsigned long long)region.start,
210                     (unsigned long long)region.end);
211         }
212         else {
213                 l = 0x0000fff0;
214                 dev_info(&bridge->dev, "  PREFETCH window: disabled\n");
215         }
216         pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
217
218         /* Set the upper 32 bits of PREF base & limit. */
219         pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
220         pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
221
222         pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
223 }
224
225 /* Check whether the bridge supports optional I/O and
226    prefetchable memory ranges. If not, the respective
227    base/limit registers must be read-only and read as 0. */
228 static void pci_bridge_check_ranges(struct pci_bus *bus)
229 {
230         u16 io;
231         u32 pmem;
232         struct pci_dev *bridge = bus->self;
233         struct resource *b_res;
234
235         b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
236         b_res[1].flags |= IORESOURCE_MEM;
237
238         pci_read_config_word(bridge, PCI_IO_BASE, &io);
239         if (!io) {
240                 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
241                 pci_read_config_word(bridge, PCI_IO_BASE, &io);
242                 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
243         }
244         if (io)
245                 b_res[0].flags |= IORESOURCE_IO;
246         /*  DECchip 21050 pass 2 errata: the bridge may miss an address
247             disconnect boundary by one PCI data phase.
248             Workaround: do not use prefetching on this device. */
249         if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
250                 return;
251         pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
252         if (!pmem) {
253                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
254                                                0xfff0fff0);
255                 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
256                 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
257         }
258         if (pmem)
259                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
260 }
261
262 /* Helper function for sizing routines: find first available
263    bus resource of a given type. Note: we intentionally skip
264    the bus resources which have already been assigned (that is,
265    have non-NULL parent resource). */
266 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
267 {
268         int i;
269         struct resource *r;
270         unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
271                                   IORESOURCE_PREFETCH;
272
273         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
274                 r = bus->resource[i];
275                 if (r == &ioport_resource || r == &iomem_resource)
276                         continue;
277                 if (r && (r->flags & type_mask) == type && !r->parent)
278                         return r;
279         }
280         return NULL;
281 }
282
283 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
284    since these windows have 4K granularity and the IO ranges
285    of non-bridge PCI devices are limited to 256 bytes.
286    We must be careful with the ISA aliasing though. */
287 static void pbus_size_io(struct pci_bus *bus)
288 {
289         struct pci_dev *dev;
290         struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
291         unsigned long size = 0, size1 = 0;
292
293         if (!b_res)
294                 return;
295
296         list_for_each_entry(dev, &bus->devices, bus_list) {
297                 int i;
298
299                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
300                         struct resource *r = &dev->resource[i];
301                         unsigned long r_size;
302
303                         if (r->parent || !(r->flags & IORESOURCE_IO))
304                                 continue;
305                         r_size = resource_size(r);
306
307                         if (r_size < 0x400)
308                                 /* Might be re-aligned for ISA */
309                                 size += r_size;
310                         else
311                                 size1 += r_size;
312                 }
313         }
314 /* To be fixed in 2.5: we should have sort of HAVE_ISA
315    flag in the struct pci_bus. */
316 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
317         size = (size & 0xff) + ((size & ~0xffUL) << 2);
318 #endif
319         size = ALIGN(size + size1, 4096);
320         if (!size) {
321                 b_res->flags = 0;
322                 return;
323         }
324         /* Alignment of the IO window is always 4K */
325         b_res->start = 4096;
326         b_res->end = b_res->start + size - 1;
327         b_res->flags |= IORESOURCE_STARTALIGN;
328 }
329
330 /* Calculate the size of the bus and minimal alignment which
331    guarantees that all child resources fit in this size. */
332 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
333 {
334         struct pci_dev *dev;
335         resource_size_t min_align, align, size;
336         resource_size_t aligns[12];     /* Alignments from 1Mb to 2Gb */
337         int order, max_order;
338         struct resource *b_res = find_free_bus_resource(bus, type);
339
340         if (!b_res)
341                 return 0;
342
343         memset(aligns, 0, sizeof(aligns));
344         max_order = 0;
345         size = 0;
346
347         list_for_each_entry(dev, &bus->devices, bus_list) {
348                 int i;
349                 
350                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
351                         struct resource *r = &dev->resource[i];
352                         resource_size_t r_size;
353
354                         if (r->parent || (r->flags & mask) != type)
355                                 continue;
356                         r_size = resource_size(r);
357                         /* For bridges size != alignment */
358                         align = resource_alignment(r);
359                         order = __ffs(align) - 20;
360                         if (order > 11) {
361                                 dev_warn(&dev->dev, "BAR %d bad alignment %llx: "
362                                          "%pR\n", i, (unsigned long long)align, r);
363                                 r->flags = 0;
364                                 continue;
365                         }
366                         size += r_size;
367                         if (order < 0)
368                                 order = 0;
369                         /* Exclude ranges with size > align from
370                            calculation of the alignment. */
371                         if (r_size == align)
372                                 aligns[order] += align;
373                         if (order > max_order)
374                                 max_order = order;
375                 }
376         }
377
378         align = 0;
379         min_align = 0;
380         for (order = 0; order <= max_order; order++) {
381                 resource_size_t align1 = 1;
382
383                 align1 <<= (order + 20);
384
385                 if (!align)
386                         min_align = align1;
387                 else if (ALIGN(align + min_align, min_align) < align1)
388                         min_align = align1 >> 1;
389                 align += aligns[order];
390         }
391         size = ALIGN(size, min_align);
392         if (!size) {
393                 b_res->flags = 0;
394                 return 1;
395         }
396         b_res->start = min_align;
397         b_res->end = size + min_align - 1;
398         b_res->flags |= IORESOURCE_STARTALIGN;
399         return 1;
400 }
401
402 static void pci_bus_size_cardbus(struct pci_bus *bus)
403 {
404         struct pci_dev *bridge = bus->self;
405         struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
406         u16 ctrl;
407
408         /*
409          * Reserve some resources for CardBus.  We reserve
410          * a fixed amount of bus space for CardBus bridges.
411          */
412         b_res[0].start = 0;
413         b_res[0].end = pci_cardbus_io_size - 1;
414         b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
415
416         b_res[1].start = 0;
417         b_res[1].end = pci_cardbus_io_size - 1;
418         b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
419
420         /*
421          * Check whether prefetchable memory is supported
422          * by this bridge.
423          */
424         pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
425         if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
426                 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
427                 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
428                 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
429         }
430
431         /*
432          * If we have prefetchable memory support, allocate
433          * two regions.  Otherwise, allocate one region of
434          * twice the size.
435          */
436         if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
437                 b_res[2].start = 0;
438                 b_res[2].end = pci_cardbus_mem_size - 1;
439                 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
440
441                 b_res[3].start = 0;
442                 b_res[3].end = pci_cardbus_mem_size - 1;
443                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
444         } else {
445                 b_res[3].start = 0;
446                 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
447                 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
448         }
449 }
450
451 void __ref pci_bus_size_bridges(struct pci_bus *bus)
452 {
453         struct pci_dev *dev;
454         unsigned long mask, prefmask;
455
456         list_for_each_entry(dev, &bus->devices, bus_list) {
457                 struct pci_bus *b = dev->subordinate;
458                 if (!b)
459                         continue;
460
461                 switch (dev->class >> 8) {
462                 case PCI_CLASS_BRIDGE_CARDBUS:
463                         pci_bus_size_cardbus(b);
464                         break;
465
466                 case PCI_CLASS_BRIDGE_PCI:
467                 default:
468                         pci_bus_size_bridges(b);
469                         break;
470                 }
471         }
472
473         /* The root bus? */
474         if (!bus->self)
475                 return;
476
477         switch (bus->self->class >> 8) {
478         case PCI_CLASS_BRIDGE_CARDBUS:
479                 /* don't size cardbuses yet. */
480                 break;
481
482         case PCI_CLASS_BRIDGE_PCI:
483                 pci_bridge_check_ranges(bus);
484         default:
485                 pbus_size_io(bus);
486                 /* If the bridge supports prefetchable range, size it
487                    separately. If it doesn't, or its prefetchable window
488                    has already been allocated by arch code, try
489                    non-prefetchable range for both types of PCI memory
490                    resources. */
491                 mask = IORESOURCE_MEM;
492                 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
493                 if (pbus_size_mem(bus, prefmask, prefmask))
494                         mask = prefmask; /* Success, size non-prefetch only. */
495                 pbus_size_mem(bus, mask, IORESOURCE_MEM);
496                 break;
497         }
498 }
499 EXPORT_SYMBOL(pci_bus_size_bridges);
500
501 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
502 {
503         struct pci_bus *b;
504         struct pci_dev *dev;
505
506         pbus_assign_resources_sorted(bus);
507
508         list_for_each_entry(dev, &bus->devices, bus_list) {
509                 b = dev->subordinate;
510                 if (!b)
511                         continue;
512
513                 pci_bus_assign_resources(b);
514
515                 switch (dev->class >> 8) {
516                 case PCI_CLASS_BRIDGE_PCI:
517                         pci_setup_bridge(b);
518                         break;
519
520                 case PCI_CLASS_BRIDGE_CARDBUS:
521                         pci_setup_cardbus(b);
522                         break;
523
524                 default:
525                         dev_info(&dev->dev, "not setting up bridge for bus "
526                                  "%04x:%02x\n", pci_domain_nr(b), b->number);
527                         break;
528                 }
529         }
530 }
531 EXPORT_SYMBOL(pci_bus_assign_resources);
532
533 static void pci_bus_dump_res(struct pci_bus *bus)
534 {
535         int i;
536
537         for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
538                 struct resource *res = bus->resource[i];
539                 if (!res || !res->end)
540                         continue;
541
542                 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %s %pR\n", i,
543                            (res->flags & IORESOURCE_IO) ? "io: " :
544                             ((res->flags & IORESOURCE_PREFETCH)? "pref mem":"mem:"),
545                            res);
546         }
547 }
548
549 static void pci_bus_dump_resources(struct pci_bus *bus)
550 {
551         struct pci_bus *b;
552         struct pci_dev *dev;
553
554
555         pci_bus_dump_res(bus);
556
557         list_for_each_entry(dev, &bus->devices, bus_list) {
558                 b = dev->subordinate;
559                 if (!b)
560                         continue;
561
562                 pci_bus_dump_resources(b);
563         }
564 }
565
566 void __init
567 pci_assign_unassigned_resources(void)
568 {
569         struct pci_bus *bus;
570
571         /* Depth first, calculate sizes and alignments of all
572            subordinate buses. */
573         list_for_each_entry(bus, &pci_root_buses, node) {
574                 pci_bus_size_bridges(bus);
575         }
576         /* Depth last, allocate resources and update the hardware. */
577         list_for_each_entry(bus, &pci_root_buses, node) {
578                 pci_bus_assign_resources(bus);
579                 pci_enable_bridges(bus);
580         }
581
582         /* dump the resource on buses */
583         list_for_each_entry(bus, &pci_root_buses, node) {
584                 pci_bus_dump_resources(bus);
585         }
586 }