ENGR00123294 MX53: 4 stripes algorithm for support resizing for big screen
[efikamx:linux-kernel.git] / include / linux / ipu.h
1 /*
2  * Copyright 2005-2010 Freescale Semiconductor, Inc.
3  */
4
5 /*
6  * The code contained herein is licensed under the GNU Lesser General
7  * Public License.  You may obtain a copy of the GNU Lesser General
8  * Public License Version 2.1 or later at the following locations:
9  *
10  * http://www.opensource.org/licenses/lgpl-license.html
11  * http://www.gnu.org/copyleft/lgpl.html
12  */
13
14 /*!
15  * @defgroup IPU MXC Image Processing Unit (IPU) Driver
16  */
17 /*!
18  * @file arch-mxc/ipu.h
19  *
20  * @brief This file contains the IPU driver API declarations.
21  *
22  * @ingroup IPU
23  */
24
25 #ifndef __ASM_ARCH_IPU_H__
26 #define __ASM_ARCH_IPU_H__
27
28 #include <linux/types.h>
29 #include <linux/videodev2.h>
30 #ifdef __KERNEL__
31 #include <linux/interrupt.h>
32 #else
33 #ifndef __cplusplus
34 typedef unsigned char bool;
35 #endif
36 #define irqreturn_t int
37 #define dma_addr_t int
38 #define u32 unsigned int
39 #define __u32 u32
40 #endif
41
42 /*!
43  * Enumeration of IPU rotation modes
44  */
45 typedef enum {
46         /* Note the enum values correspond to BAM value */
47         IPU_ROTATE_NONE = 0,
48         IPU_ROTATE_VERT_FLIP = 1,
49         IPU_ROTATE_HORIZ_FLIP = 2,
50         IPU_ROTATE_180 = 3,
51         IPU_ROTATE_90_RIGHT = 4,
52         IPU_ROTATE_90_RIGHT_VFLIP = 5,
53         IPU_ROTATE_90_RIGHT_HFLIP = 6,
54         IPU_ROTATE_90_LEFT = 7,
55 } ipu_rotate_mode_t;
56
57 /*!
58  * Enumeration of Post Filter modes
59  */
60 typedef enum {
61         PF_DISABLE_ALL = 0,
62         PF_MPEG4_DEBLOCK = 1,
63         PF_MPEG4_DERING = 2,
64         PF_MPEG4_DEBLOCK_DERING = 3,
65         PF_H264_DEBLOCK = 4,
66 } pf_operation_t;
67
68 /*!
69  * Enumeration of Synchronous (Memory-less) panel types
70  */
71 typedef enum {
72         IPU_PANEL_SHARP_TFT,
73         IPU_PANEL_TFT,
74 } ipu_panel_t;
75
76 /*!
77  * Enumeration of VDI MOTION select
78  */
79 typedef enum {
80         MED_MOTION = 0,
81         LOW_MOTION = 1,
82         HIGH_MOTION = 2,
83 } ipu_motion_sel;
84
85 /*  IPU Pixel format definitions */
86 /*  Four-character-code (FOURCC) */
87 #define fourcc(a, b, c, d)\
88         (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
89
90 /*!
91  * @name IPU Pixel Formats
92  *
93  * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
94  * the same used by V4L2 API.
95  */
96
97 /*! @{ */
98 /*! @name Generic or Raw Data Formats */
99 /*! @{ */
100 #define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')  /*!< IPU Generic Data */
101 #define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')       /*!< IPU Generic Data */
102 #define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')  /*!< IPU Generic Data */
103 #define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')  /*!< IPU Generic Data */
104 /*! @} */
105 /*! @name RGB Formats */
106 /*! @{ */
107 #define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')  /*!<  8  RGB-3-3-2    */
108 #define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')  /*!< 16  RGB-5-5-5    */
109 #define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')  /*!< 1 6  RGB-5-6-5   */
110 #define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')  /*!< 18  RGB-6-6-6    */
111 #define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')  /*!< 18  BGR-6-6-6    */
112 #define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')  /*!< 24  BGR-8-8-8    */
113 #define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')  /*!< 24  RGB-8-8-8    */
114 #define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')  /*!< 32  BGR-8-8-8-8  */
115 #define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')  /*!< 32  BGR-8-8-8-8  */
116 #define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')  /*!< 32  RGB-8-8-8-8  */
117 #define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')  /*!< 32  RGB-8-8-8-8  */
118 #define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')  /*!< 32  ABGR-8-8-8-8 */
119 /*! @} */
120 /*! @name YUV Interleaved Formats */
121 /*! @{ */
122 #define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')  /*!< 16 YUV 4:2:2 */
123 #define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')  /*!< 16 YUV 4:2:2 */
124 #define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')  /*!< 12 YUV 4:1:1 */
125 #define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')  /*!< 24 YUV 4:4:4 */
126 /* two planes -- one Y, one Cb + Cr interleaved  */
127 #define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
128 /*! @} */
129 /*! @name YUV Planar Formats */
130 /*! @{ */
131 #define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')  /*!< 8  Greyscale */
132 #define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')  /*!< 9  YVU 4:1:0 */
133 #define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')  /*!< 9  YUV 4:1:0 */
134 #define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')  /*!< 12 YVU 4:2:0 */
135 #define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')  /*!< 12 YUV 4:2:0 */
136 #define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
137 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')  /*!< 16 YVU 4:2:2 */
138 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')  /*!< 16 YUV 4:2:2 */
139 /*! @} */
140
141 /* IPU Driver channels definitions.     */
142 /* Note these are different from IDMA channels */
143 #ifdef CONFIG_MXC_IPU_V1
144 #define _MAKE_CHAN(num, in, out, sec)    ((num << 24) | (sec << 16) | (out << 8) | in)
145 #define IPU_CHAN_ID(ch)         (ch >> 24)
146 #define IPU_CHAN_SEC_DMA(ch)    ((uint32_t) (ch >> 16) & 0xFF)
147 #define IPU_CHAN_OUT_DMA(ch)    ((uint32_t) (ch >> 8) & 0xFF)
148 #define IPU_CHAN_IN_DMA(ch)     ((uint32_t) (ch & 0xFF))
149
150 #else
151 #define IPU_MAX_CH      32
152 #define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
153         ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
154 #define _MAKE_ALT_CHAN(ch)              (ch | (IPU_MAX_CH << 24))
155 #define IPU_CHAN_ID(ch)                 (ch >> 24)
156 #define IPU_CHAN_ALT(ch)                (ch & 0x02000000)
157 #define IPU_CHAN_ALPHA_IN_DMA(ch)       ((uint32_t) (ch >> 6) & 0x3F)
158 #define IPU_CHAN_GRAPH_IN_DMA(ch)       ((uint32_t) (ch >> 12) & 0x3F)
159 #define IPU_CHAN_VIDEO_IN_DMA(ch)       ((uint32_t) (ch >> 18) & 0x3F)
160 #define IPU_CHAN_OUT_DMA(ch)            ((uint32_t) (ch & 0x3F))
161 #define NO_DMA 0x3F
162 #define ALT     1
163 #endif
164 /*!
165  * Enumeration of IPU logical channels. An IPU logical channel is defined as a
166  * combination of an input (memory to IPU), output (IPU to memory), and/or
167  * secondary input IDMA channels and in some cases an Image Converter task.
168  * Some channels consist of only an input or output.
169  */
170 typedef enum {
171         CHAN_NONE = -1,
172 #ifdef CONFIG_MXC_IPU_V1
173         CSI_MEM = _MAKE_CHAN(1, 0xFF, 7, 0xFF), /*!< CSI raw sensor data to memory */
174
175         CSI_PRP_ENC_MEM = _MAKE_CHAN(2, 0xFF, 0, 0xFF), /*!< CSI to IC Encoder PreProcessing to Memory */
176         MEM_PRP_ENC_MEM = _MAKE_CHAN(3, 6, 0, 0xFF),    /*!< Memory to IC Encoder PreProcessing to Memory */
177         MEM_ROT_ENC_MEM = _MAKE_CHAN(4, 10, 8, 0xFF),   /*!< Memory to IC Encoder Rotation to Memory */
178
179         CSI_PRP_VF_MEM = _MAKE_CHAN(5, 0xFF, 1, 0xFF),  /*!< CSI to IC Viewfinder PreProcessing to Memory */
180         CSI_PRP_VF_ADC = _MAKE_CHAN(6, 0xFF, 1, 0xFF),  /*!< CSI to IC Viewfinder PreProcessing to ADC */
181         MEM_PRP_VF_MEM = _MAKE_CHAN(7, 6, 1, 3),        /*!< Memory to IC Viewfinder PreProcessing to Memory */
182         MEM_PRP_VF_ADC = _MAKE_CHAN(8, 6, 1, 3),        /*!< Memory to IC Viewfinder PreProcessing to ADC */
183         MEM_ROT_VF_MEM = _MAKE_CHAN(9, 11, 9, 0xFF),    /*!< Memory to IC Viewfinder Rotation to Memory */
184
185         MEM_PP_MEM = _MAKE_CHAN(10, 5, 2, 4),   /*!< Memory to IC PostProcessing to Memory */
186         MEM_ROT_PP_MEM = _MAKE_CHAN(11, 13, 12, 0xFF),  /*!< Memory to IC PostProcessing Rotation to Memory */
187         MEM_PP_ADC = _MAKE_CHAN(12, 5, 2, 4),   /*!< Memory to IC PostProcessing to ADC */
188
189         MEM_SDC_BG = _MAKE_CHAN(14, 14, 0xFF, 0xFF),    /*!< Memory to SDC Background plane */
190         MEM_SDC_FG = _MAKE_CHAN(15, 15, 0xFF, 0xFF),    /*!< Memory to SDC Foreground plane */
191         MEM_SDC_MASK = _MAKE_CHAN(16, 16, 0xFF, 0xFF),  /*!< Memory to SDC Mask */
192
193         MEM_BG_SYNC = MEM_SDC_BG,
194         MEM_FG_SYNC = MEM_SDC_FG,
195
196         ADC_SYS1 = _MAKE_CHAN(17, 18, 22, 20),  /*!< Memory to ADC System Channel 1 */
197         ADC_SYS2 = _MAKE_CHAN(18, 19, 23, 21),  /*!< Memory to ADC System Channel 2 */
198
199         MEM_PF_Y_MEM = _MAKE_CHAN(19, 26, 29, 24),      /*!< Y and PF Memory to Post-filter to Y Memory */
200         MEM_PF_U_MEM = _MAKE_CHAN(20, 27, 30, 25),      /*!< U and PF Memory to Post-filter to U Memory */
201         MEM_PF_V_MEM = _MAKE_CHAN(21, 28, 31, 0xFF),    /*!< V Memory to Post-filter to V Memory */
202
203         MEM_DC_SYNC = CHAN_NONE,
204         DIRECT_ASYNC0 = CHAN_NONE,
205         DIRECT_ASYNC1 = CHAN_NONE,
206         MEM_VDI_PRP_VF_MEM_P = CHAN_NONE,
207         MEM_VDI_PRP_VF_MEM = CHAN_NONE,
208         MEM_VDI_PRP_VF_MEM_N = CHAN_NONE,
209 #else
210         MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
211         MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
212         MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
213
214         MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
215         MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
216         MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
217
218         MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
219         MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
220         MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
221         MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
222
223         MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
224         MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
225         MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
226         MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
227
228         DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
229         DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
230
231         CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
232         CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
233         CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
234         CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
235
236         CSI_MEM = CSI_MEM0,
237
238         CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
239         CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
240
241         MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
242         MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
243         MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
244
245         MEM_PP_ADC = CHAN_NONE,
246         ADC_SYS2 = CHAN_NONE,
247 #endif
248
249 } ipu_channel_t;
250
251 /*!
252  * Enumeration of types of buffers for a logical channel.
253  */
254 typedef enum {
255         IPU_OUTPUT_BUFFER = 0,  /*!< Buffer for output from IPU */
256         IPU_ALPHA_IN_BUFFER = 1,        /*!< Buffer for input to IPU */
257         IPU_GRAPH_IN_BUFFER = 2,        /*!< Buffer for input to IPU */
258         IPU_VIDEO_IN_BUFFER = 3,        /*!< Buffer for input to IPU */
259         IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
260         IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
261 } ipu_buffer_t;
262
263 #define IPU_PANEL_SERIAL                1
264 #define IPU_PANEL_PARALLEL              2
265
266 /*!
267  * Enumeration of DI ports for ADC.
268  */
269 typedef enum {
270         DISP0,
271         DISP1,
272         DISP2,
273         DISP3
274 } display_port_t;
275
276 /*!
277  * Enumeration of ADC channel operation mode.
278  */
279 typedef enum {
280         Disable,
281         WriteTemplateNonSeq,
282         ReadTemplateNonSeq,
283         WriteTemplateUnCon,
284         ReadTemplateUnCon,
285         WriteDataWithRS,
286         WriteDataWoRS,
287         WriteCmd
288 } mcu_mode_t;
289
290 /*!
291  * Enumeration of ADC channel addressing mode.
292  */
293 typedef enum {
294         FullWoBE,
295         FullWithBE,
296         XY
297 } display_addressing_t;
298
299 /*!
300  * Union of initialization parameters for a logical channel.
301  */
302 typedef union {
303         struct {
304                 uint32_t csi;
305                 bool mipi_en;
306                 uint32_t mipi_id;
307         } csi_mem;
308         struct {
309                 uint32_t in_width;
310                 uint32_t in_height;
311                 uint32_t in_pixel_fmt;
312                 uint32_t out_width;
313                 uint32_t out_height;
314                 uint32_t out_pixel_fmt;
315                 uint32_t csi;
316         } csi_prp_enc_mem;
317         struct {
318                 uint32_t in_width;
319                 uint32_t in_height;
320                 uint32_t in_pixel_fmt;
321                 uint32_t out_width;
322                 uint32_t out_height;
323                 uint32_t out_pixel_fmt;
324                 uint32_t outh_resize_ratio;
325                 uint32_t outv_resize_ratio;
326         } mem_prp_enc_mem;
327         struct {
328                 uint32_t in_width;
329                 uint32_t in_height;
330                 uint32_t in_pixel_fmt;
331                 uint32_t out_width;
332                 uint32_t out_height;
333                 uint32_t out_pixel_fmt;
334         } mem_rot_enc_mem;
335         struct {
336                 uint32_t in_width;
337                 uint32_t in_height;
338                 uint32_t in_pixel_fmt;
339                 uint32_t out_width;
340                 uint32_t out_height;
341                 uint32_t out_pixel_fmt;
342                 bool graphics_combine_en;
343                 bool global_alpha_en;
344                 bool key_color_en;
345                 uint32_t csi;
346         } csi_prp_vf_mem;
347         struct {
348                 uint32_t in_width;
349                 uint32_t in_height;
350                 uint32_t in_pixel_fmt;
351                 uint32_t out_width;
352                 uint32_t out_height;
353                 uint32_t out_pixel_fmt;
354                 bool graphics_combine_en;
355                 bool global_alpha_en;
356                 bool key_color_en;
357                 display_port_t disp;
358                 uint32_t out_left;
359                 uint32_t out_top;
360         } csi_prp_vf_adc;
361         struct {
362                 uint32_t in_width;
363                 uint32_t in_height;
364                 uint32_t in_pixel_fmt;
365                 uint32_t out_width;
366                 uint32_t out_height;
367                 uint32_t out_pixel_fmt;
368                 uint32_t outh_resize_ratio;
369                 uint32_t outv_resize_ratio;
370                 bool graphics_combine_en;
371                 bool global_alpha_en;
372                 bool key_color_en;
373                 uint32_t in_g_pixel_fmt;
374                 uint8_t alpha;
375                 uint32_t key_color;
376                 bool alpha_chan_en;
377                 ipu_motion_sel motion_sel;
378                 enum v4l2_field field_fmt;
379         } mem_prp_vf_mem;
380         struct {
381                 uint32_t temp;
382         } mem_prp_vf_adc;
383         struct {
384                 uint32_t temp;
385         } mem_rot_vf_mem;
386         struct {
387                 uint32_t in_width;
388                 uint32_t in_height;
389                 uint32_t in_pixel_fmt;
390                 uint32_t out_width;
391                 uint32_t out_height;
392                 uint32_t out_pixel_fmt;
393                 uint32_t outv_resize_ratio;
394                 uint32_t outh_resize_ratio;
395                 bool graphics_combine_en;
396                 bool global_alpha_en;
397                 bool key_color_en;
398                 uint32_t in_g_pixel_fmt;
399                 uint8_t alpha;
400                 uint32_t key_color;
401                 bool alpha_chan_en;
402         } mem_pp_mem;
403         struct {
404                 uint32_t temp;
405         } mem_rot_mem;
406         struct {
407                 uint32_t in_width;
408                 uint32_t in_height;
409                 uint32_t in_pixel_fmt;
410                 uint32_t out_width;
411                 uint32_t out_height;
412                 uint32_t out_pixel_fmt;
413                 bool graphics_combine_en;
414                 bool global_alpha_en;
415                 bool key_color_en;
416                 display_port_t disp;
417                 uint32_t out_left;
418                 uint32_t out_top;
419         } mem_pp_adc;
420         struct {
421                 pf_operation_t operation;
422         } mem_pf_mem;
423         struct {
424                 uint32_t di;
425                 bool interlaced;
426         } mem_dc_sync;
427         struct {
428                 uint32_t temp;
429         } mem_sdc_fg;
430         struct {
431                 uint32_t di;
432                 bool interlaced;
433                 uint32_t in_pixel_fmt;
434                 uint32_t out_pixel_fmt;
435                 bool alpha_chan_en;
436         } mem_dp_bg_sync;
437         struct {
438                 uint32_t temp;
439         } mem_sdc_bg;
440         struct {
441                 uint32_t di;
442                 bool interlaced;
443                 uint32_t in_pixel_fmt;
444                 uint32_t out_pixel_fmt;
445                 bool alpha_chan_en;
446         } mem_dp_fg_sync;
447         struct {
448                 uint32_t di;
449         } direct_async;
450         struct {
451                 display_port_t disp;
452                 mcu_mode_t ch_mode;
453                 uint32_t out_left;
454                 uint32_t out_top;
455         } adc_sys1;
456         struct {
457                 display_port_t disp;
458                 mcu_mode_t ch_mode;
459                 uint32_t out_left;
460                 uint32_t out_top;
461         } adc_sys2;
462 } ipu_channel_params_t;
463
464 /*!
465  * Enumeration of IPU interrupt sources.
466  */
467 enum ipu_irq_line {
468 #ifdef CONFIG_MXC_IPU_V1
469         IPU_IRQ_DC_FC_1 = -1,
470
471         IPU_IRQ_PRP_ENC_OUT_EOF = 0,
472         IPU_IRQ_PRP_VF_OUT_EOF = 1,
473         IPU_IRQ_PP_OUT_EOF = 2,
474         IPU_IRQ_PRP_GRAPH_IN_EOF = 3,
475         IPU_IRQ_PP_GRAPH_IN_EOF = 4,
476         IPU_IRQ_PP_IN_EOF = 5,
477         IPU_IRQ_PRP_IN_EOF = 6,
478         IPU_IRQ_SENSOR_OUT_EOF = 7,
479         IPU_IRQ_CSI0_OUT_EOF = IPU_IRQ_SENSOR_OUT_EOF,
480         IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 8,
481         IPU_IRQ_PRP_VF_ROT_OUT_EOF = 9,
482         IPU_IRQ_PRP_ENC_ROT_IN_EOF = 10,
483         IPU_IRQ_PRP_VF_ROT_IN_EOF = 11,
484         IPU_IRQ_PP_ROT_OUT_EOF = 12,
485         IPU_IRQ_PP_ROT_IN_EOF = 13,
486         IPU_IRQ_BG_SYNC_EOF = 14,
487         IPU_IRQ_SDC_BG_EOF = IPU_IRQ_BG_SYNC_EOF,
488         IPU_IRQ_FG_SYNC_EOF = 15,
489         IPU_IRQ_SDC_FG_EOF = IPU_IRQ_FG_SYNC_EOF,
490         IPU_IRQ_SDC_MASK_EOF = 16,
491         IPU_IRQ_SDC_BG_PART_EOF = 17,
492         IPU_IRQ_ADC_SYS1_WR_EOF = 18,
493         IPU_IRQ_ADC_SYS2_WR_EOF = 19,
494         IPU_IRQ_ADC_SYS1_CMD_EOF = 20,
495         IPU_IRQ_ADC_SYS2_CMD_EOF = 21,
496         IPU_IRQ_ADC_SYS1_RD_EOF = 22,
497         IPU_IRQ_ADC_SYS2_RD_EOF = 23,
498         IPU_IRQ_PF_QP_IN_EOF = 24,
499         IPU_IRQ_PF_BSP_IN_EOF = 25,
500         IPU_IRQ_PF_Y_IN_EOF = 26,
501         IPU_IRQ_PF_U_IN_EOF = 27,
502         IPU_IRQ_PF_V_IN_EOF = 28,
503         IPU_IRQ_PF_Y_OUT_EOF = 29,
504         IPU_IRQ_PF_U_OUT_EOF = 30,
505         IPU_IRQ_PF_V_OUT_EOF = 31,
506
507         IPU_IRQ_PRP_ENC_OUT_NF = 32,
508         IPU_IRQ_PRP_VF_OUT_NF = 33,
509         IPU_IRQ_PP_OUT_NF = 34,
510         IPU_IRQ_PRP_GRAPH_IN_NF = 35,
511         IPU_IRQ_PP_GRAPH_IN_NF = 36,
512         IPU_IRQ_PP_IN_NF = 37,
513         IPU_IRQ_PRP_IN_NF = 38,
514         IPU_IRQ_SENSOR_OUT_NF = 39,
515         IPU_IRQ_PRP_ENC_ROT_OUT_NF = 40,
516         IPU_IRQ_PRP_VF_ROT_OUT_NF = 41,
517         IPU_IRQ_PRP_ENC_ROT_IN_NF = 42,
518         IPU_IRQ_PRP_VF_ROT_IN_NF = 43,
519         IPU_IRQ_PP_ROT_OUT_NF = 44,
520         IPU_IRQ_PP_ROT_IN_NF = 45,
521         IPU_IRQ_SDC_FG_NF = 46,
522         IPU_IRQ_SDC_BG_NF = 47,
523         IPU_IRQ_SDC_MASK_NF = 48,
524         IPU_IRQ_SDC_BG_PART_NF = 49,
525         IPU_IRQ_ADC_SYS1_WR_NF = 50,
526         IPU_IRQ_ADC_SYS2_WR_NF = 51,
527         IPU_IRQ_ADC_SYS1_CMD_NF = 52,
528         IPU_IRQ_ADC_SYS2_CMD_NF = 53,
529         IPU_IRQ_ADC_SYS1_RD_NF = 54,
530         IPU_IRQ_ADC_SYS2_RD_NF = 55,
531         IPU_IRQ_PF_QP_IN_NF = 56,
532         IPU_IRQ_PF_BSP_IN_NF = 57,
533         IPU_IRQ_PF_Y_IN_NF = 58,
534         IPU_IRQ_PF_U_IN_NF = 59,
535         IPU_IRQ_PF_V_IN_NF = 60,
536         IPU_IRQ_PF_Y_OUT_NF = 61,
537         IPU_IRQ_PF_U_OUT_NF = 62,
538         IPU_IRQ_PF_V_OUT_NF = 63,
539
540         IPU_IRQ_BREAKRQ = 64,
541         IPU_IRQ_SDC_BG_OUT_EOF = 65,
542         IPU_IRQ_BG_SF_END = IPU_IRQ_SDC_BG_OUT_EOF,
543         IPU_IRQ_SDC_FG_OUT_EOF = 66,
544         IPU_IRQ_SDC_MASK_OUT_EOF = 67,
545         IPU_IRQ_ADC_SERIAL_DATA_OUT = 68,
546         IPU_IRQ_SENSOR_NF = 69,
547         IPU_IRQ_SENSOR_EOF = 70,
548         IPU_IRQ_SDC_DISP3_VSYNC = 80,
549         IPU_IRQ_ADC_DISP0_VSYNC = 81,
550         IPU_IRQ_ADC_DISP12_VSYNC = 82,
551         IPU_IRQ_ADC_PRP_EOF = 83,
552         IPU_IRQ_ADC_PP_EOF = 84,
553         IPU_IRQ_ADC_SYS1_EOF = 85,
554         IPU_IRQ_ADC_SYS2_EOF = 86,
555
556         IPU_IRQ_PRP_ENC_OUT_NFB4EOF_ERR = 96,
557         IPU_IRQ_PRP_VF_OUT_NFB4EOF_ERR = 97,
558         IPU_IRQ_PP_OUT_NFB4EOF_ERR = 98,
559         IPU_IRQ_PRP_GRAPH_IN_NFB4EOF_ERR = 99,
560         IPU_IRQ_PP_GRAPH_IN_NFB4EOF_ERR = 100,
561         IPU_IRQ_PP_IN_NFB4EOF_ERR = 101,
562         IPU_IRQ_PRP_IN_NFB4EOF_ERR = 102,
563         IPU_IRQ_SENSOR_OUT_NFB4EOF_ERR = 103,
564         IPU_IRQ_PRP_ENC_ROT_OUT_NFB4EOF_ERR = 104,
565         IPU_IRQ_PRP_VF_ROT_OUT_NFB4EOF_ERR = 105,
566         IPU_IRQ_PRP_ENC_ROT_IN_NFB4EOF_ERR = 106,
567         IPU_IRQ_PRP_VF_ROT_IN_NFB4EOF_ERR = 107,
568         IPU_IRQ_PP_ROT_OUT_NFB4EOF_ERR = 108,
569         IPU_IRQ_PP_ROT_IN_NFB4EOF_ERR = 109,
570         IPU_IRQ_SDC_FG_NFB4EOF_ERR = 110,
571         IPU_IRQ_SDC_BG_NFB4EOF_ERR = 111,
572         IPU_IRQ_SDC_MASK_NFB4EOF_ERR = 112,
573         IPU_IRQ_SDC_BG_PART_NFB4EOF_ERR = 113,
574         IPU_IRQ_ADC_SYS1_WR_NFB4EOF_ERR = 114,
575         IPU_IRQ_ADC_SYS2_WR_NFB4EOF_ERR = 115,
576         IPU_IRQ_ADC_SYS1_CMD_NFB4EOF_ERR = 116,
577         IPU_IRQ_ADC_SYS2_CMD_NFB4EOF_ERR = 117,
578         IPU_IRQ_ADC_SYS1_RD_NFB4EOF_ERR = 118,
579         IPU_IRQ_ADC_SYS2_RD_NFB4EOF_ERR = 119,
580         IPU_IRQ_PF_QP_IN_NFB4EOF_ERR = 120,
581         IPU_IRQ_PF_BSP_IN_NFB4EOF_ERR = 121,
582         IPU_IRQ_PF_Y_IN_NFB4EOF_ERR = 122,
583         IPU_IRQ_PF_U_IN_NFB4EOF_ERR = 123,
584         IPU_IRQ_PF_V_IN_NFB4EOF_ERR = 124,
585         IPU_IRQ_PF_Y_OUT_NFB4EOF_ERR = 125,
586         IPU_IRQ_PF_U_OUT_NFB4EOF_ERR = 126,
587         IPU_IRQ_PF_V_OUT_NFB4EOF_ERR = 127,
588
589         IPU_IRQ_BAYER_BUFOVF_ERR = 128,
590         IPU_IRQ_ENC_BUFOVF_ERR = 129,
591         IPU_IRQ_VF_BUFOVF_ERR = 130,
592         IPU_IRQ_ADC_PP_TEAR_ERR = 131,
593         IPU_IRQ_ADC_SYS1_TEAR_ERR = 132,
594         IPU_IRQ_ADC_SYS2_TEAR_ERR = 133,
595         IPU_IRQ_SDC_BGD_ERR = 134,
596         IPU_IRQ_SDC_FGD_ERR = 135,
597         IPU_IRQ_SDC_MASKD_ERR = 136,
598         IPU_IRQ_BAYER_FRM_LOST_ERR = 137,
599         IPU_IRQ_ENC_FRM_LOST_ERR = 138,
600         IPU_IRQ_VF_FRM_LOST_ERR = 139,
601         IPU_IRQ_ADC_LOCK_ERR = 140,
602         IPU_IRQ_DI_LLA_LOCK_ERR = 141,
603         IPU_IRQ_AHB_M1_ERR = 142,
604         IPU_IRQ_AHB_M12_ERR = 143,
605 #else
606         IPU_IRQ_CSI0_OUT_EOF = 0,
607         IPU_IRQ_CSI1_OUT_EOF = 1,
608         IPU_IRQ_CSI2_OUT_EOF = 2,
609         IPU_IRQ_CSI3_OUT_EOF = 3,
610         IPU_IRQ_PP_IN_EOF = 11,
611         IPU_IRQ_PRP_IN_EOF = 12,
612         IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
613         IPU_IRQ_PP_GRAPH_IN_EOF = 15,
614         IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
615         IPU_IRQ_PP_ALPHA_IN_EOF = 18,
616         IPU_IRQ_PRP_ENC_OUT_EOF = 20,
617         IPU_IRQ_PRP_VF_OUT_EOF = 21,
618         IPU_IRQ_PP_OUT_EOF = 22,
619         IPU_IRQ_BG_SYNC_EOF = 23,
620         IPU_IRQ_BG_ASYNC_EOF = 24,
621         IPU_IRQ_FG_SYNC_EOF = 27,
622         IPU_IRQ_DC_SYNC_EOF = 28,
623         IPU_IRQ_FG_ASYNC_EOF = 29,
624         IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
625
626         IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
627         IPU_IRQ_DC_READ_EOF = 40,
628         IPU_IRQ_DC_ASYNC_EOF = 41,
629         IPU_IRQ_DC_CMD1_EOF = 42,
630         IPU_IRQ_DC_CMD2_EOF = 43,
631         IPU_IRQ_DC_MASK_EOF = 44,
632         IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
633         IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
634         IPU_IRQ_PP_ROT_IN_EOF = 47,
635         IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
636         IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
637         IPU_IRQ_PP_ROT_OUT_EOF = 50,
638         IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
639         IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
640
641         IPU_IRQ_DP_SF_START = 448 + 2,
642         IPU_IRQ_DP_SF_END = 448 + 3,
643         IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
644         IPU_IRQ_DC_FC_0 = 448 + 8,
645         IPU_IRQ_DC_FC_1 = 448 + 9,
646         IPU_IRQ_DC_FC_2 = 448 + 10,
647         IPU_IRQ_DC_FC_3 = 448 + 11,
648         IPU_IRQ_DC_FC_4 = 448 + 12,
649         IPU_IRQ_DC_FC_6 = 448 + 13,
650         IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
651         IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
652 #endif
653
654         IPU_IRQ_COUNT
655 };
656
657 /*!
658  * Bitfield of Display Interface signal polarities.
659  */
660 typedef struct {
661         unsigned datamask_en:1;
662         unsigned ext_clk:1;
663         unsigned interlaced:1;
664         unsigned odd_field_first:1;
665         unsigned clksel_en:1;
666         unsigned clkidle_en:1;
667         unsigned data_pol:1;    /* true = inverted */
668         unsigned clk_pol:1;     /* true = rising edge */
669         unsigned enable_pol:1;
670         unsigned Hsync_pol:1;   /* true = active high */
671         unsigned Vsync_pol:1;
672 } ipu_di_signal_cfg_t;
673
674 /*!
675  * Bitfield of CSI signal polarities and modes.
676  */
677
678 typedef struct {
679         unsigned data_width:4;
680         unsigned clk_mode:3;
681         unsigned ext_vsync:1;
682         unsigned Vsync_pol:1;
683         unsigned Hsync_pol:1;
684         unsigned pixclk_pol:1;
685         unsigned data_pol:1;
686         unsigned sens_clksrc:1;
687         unsigned pack_tight:1;
688         unsigned force_eof:1;
689         unsigned data_en_pol:1;
690         unsigned data_fmt;
691         unsigned csi;
692         unsigned mclk;
693 } ipu_csi_signal_cfg_t;
694
695 /*!
696  * Enumeration of CSI data bus widths.
697  */
698 enum {
699         IPU_CSI_DATA_WIDTH_4,
700         IPU_CSI_DATA_WIDTH_8,
701         IPU_CSI_DATA_WIDTH_10,
702         IPU_CSI_DATA_WIDTH_16,
703 };
704
705 /*!
706  * Enumeration of CSI clock modes.
707  */
708 enum {
709         IPU_CSI_CLK_MODE_GATED_CLK,
710         IPU_CSI_CLK_MODE_NONGATED_CLK,
711         IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
712         IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
713         IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
714         IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
715         IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
716         IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
717 };
718
719 enum {
720         IPU_CSI_MIPI_DI0,
721         IPU_CSI_MIPI_DI1,
722         IPU_CSI_MIPI_DI2,
723         IPU_CSI_MIPI_DI3,
724 };
725
726 typedef enum {
727         RGB,
728         YCbCr,
729         YUV
730 } ipu_color_space_t;
731
732 /*!
733  * Enumeration of ADC vertical sync mode.
734  */
735 typedef enum {
736         VsyncNone,
737         VsyncInternal,
738         VsyncCSI,
739         VsyncExternal
740 } vsync_t;
741
742 typedef enum {
743         DAT,
744         CMD
745 } cmddata_t;
746
747 /*!
748  * Enumeration of ADC display update mode.
749  */
750 typedef enum {
751         IPU_ADC_REFRESH_NONE,
752         IPU_ADC_AUTO_REFRESH,
753         IPU_ADC_AUTO_REFRESH_SNOOP,
754         IPU_ADC_SNOOPING,
755 } ipu_adc_update_mode_t;
756
757 /*!
758  * Enumeration of ADC display interface types (serial or parallel).
759  */
760 enum {
761         IPU_ADC_IFC_MODE_SYS80_TYPE1,
762         IPU_ADC_IFC_MODE_SYS80_TYPE2,
763         IPU_ADC_IFC_MODE_SYS68K_TYPE1,
764         IPU_ADC_IFC_MODE_SYS68K_TYPE2,
765         IPU_ADC_IFC_MODE_3WIRE_SERIAL,
766         IPU_ADC_IFC_MODE_4WIRE_SERIAL,
767         IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
768         IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
769 };
770
771 enum {
772         IPU_ADC_IFC_WIDTH_8,
773         IPU_ADC_IFC_WIDTH_16,
774 };
775
776 /*!
777  * Enumeration of ADC display interface burst mode.
778  */
779 enum {
780         IPU_ADC_BURST_WCS,
781         IPU_ADC_BURST_WBLCK,
782         IPU_ADC_BURST_NONE,
783         IPU_ADC_BURST_SERIAL,
784 };
785
786 /*!
787  * Enumeration of ADC display interface RW signal timing modes.
788  */
789 enum {
790         IPU_ADC_SER_NO_RW,
791         IPU_ADC_SER_RW_BEFORE_RS,
792         IPU_ADC_SER_RW_AFTER_RS,
793 };
794
795 /*!
796  * Bitfield of ADC signal polarities and modes.
797  */
798 typedef struct {
799         unsigned data_pol:1;
800         unsigned clk_pol:1;
801         unsigned cs_pol:1;
802         unsigned rs_pol:1;
803         unsigned addr_pol:1;
804         unsigned read_pol:1;
805         unsigned write_pol:1;
806         unsigned Vsync_pol:1;
807         unsigned burst_pol:1;
808         unsigned burst_mode:2;
809         unsigned ifc_mode:3;
810         unsigned ifc_width:5;
811         unsigned ser_preamble_len:4;
812         unsigned ser_preamble:8;
813         unsigned ser_rw_mode:2;
814 } ipu_adc_sig_cfg_t;
815
816 /*!
817  * Enumeration of ADC template commands.
818  */
819 enum {
820         RD_DATA,
821         RD_ACK,
822         RD_WAIT,
823         WR_XADDR,
824         WR_YADDR,
825         WR_ADDR,
826         WR_CMND,
827         WR_DATA,
828 };
829
830 /*!
831  * Enumeration of ADC template command flow control.
832  */
833 enum {
834         SINGLE_STEP,
835         PAUSE,
836         STOP,
837 };
838
839
840 /*Define template constants*/
841 #define     ATM_ADDR_RANGE      0x20    /*offset address of DISP */
842 #define     TEMPLATE_BUF_SIZE   0x20    /*size of template */
843
844 /*!
845  * Define to create ADC template command entry.
846  */
847 #define ipu_adc_template_gen(oc, rs, fc, dat) ( ((rs) << 29) | ((fc) << 27) | \
848                                                 ((oc) << 24) | (dat) )
849
850 typedef struct {
851         u32 reg;
852         u32 value;
853 } ipu_lpmc_reg_t;
854
855 #define IPU_LPMC_REG_READ       0x80000000L
856
857 #define CSI_MCLK_VF  1
858 #define CSI_MCLK_ENC 2
859 #define CSI_MCLK_RAW 4
860 #define CSI_MCLK_I2C 8
861
862 /* Common IPU API */
863 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t * params);
864 void ipu_uninit_channel(ipu_channel_t channel);
865
866 static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
867 {
868 #ifdef CONFIG_MXC_IPU_V3D
869         return (rot < IPU_ROTATE_HORIZ_FLIP);
870 #else
871         return (rot < IPU_ROTATE_90_RIGHT);
872 #endif
873 }
874
875 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
876                                 uint32_t pixel_fmt,
877                                 uint16_t width, uint16_t height,
878                                 uint32_t stride,
879                                 ipu_rotate_mode_t rot_mode,
880                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
881                                 uint32_t u_offset, uint32_t v_offset);
882
883 int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
884                                   uint32_t bufNum, dma_addr_t phyaddr);
885
886 int32_t ipu_update_channel_offset(ipu_channel_t channel, ipu_buffer_t type,
887                                 uint32_t pixel_fmt,
888                                 uint16_t width, uint16_t height,
889                                 uint32_t stride,
890                                 uint32_t u, uint32_t v,
891                                 uint32_t vertical_offset, uint32_t horizontal_offset);
892
893 int32_t ipu_select_buffer(ipu_channel_t channel,
894                           ipu_buffer_t type, uint32_t bufNum);
895 int32_t ipu_select_multi_vdi_buffer(uint32_t bufNum);
896
897 int32_t ipu_link_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch);
898 int32_t ipu_unlink_channels(ipu_channel_t src_ch, ipu_channel_t dest_ch);
899
900 int32_t ipu_is_channel_busy(ipu_channel_t channel);
901 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
902                 uint32_t bufNum);
903 uint32_t ipu_get_cur_buffer_idx(ipu_channel_t channel, ipu_buffer_t type);
904 int32_t ipu_enable_channel(ipu_channel_t channel);
905 int32_t ipu_disable_channel(ipu_channel_t channel, bool wait_for_stop);
906 int32_t ipu_swap_channel(ipu_channel_t from_ch, ipu_channel_t to_ch);
907
908 int32_t ipu_enable_csi(uint32_t csi);
909 int32_t ipu_disable_csi(uint32_t csi);
910
911 int ipu_lowpwr_display_enable(void);
912 int ipu_lowpwr_display_disable(void);
913
914 void ipu_enable_irq(uint32_t irq);
915 void ipu_disable_irq(uint32_t irq);
916 void ipu_clear_irq(uint32_t irq);
917 int ipu_request_irq(uint32_t irq,
918                     irqreturn_t(*handler) (int, void *),
919                     uint32_t irq_flags, const char *devname, void *dev_id);
920 void ipu_free_irq(uint32_t irq, void *dev_id);
921 bool ipu_get_irq_status(uint32_t irq);
922 void ipu_set_csc_coefficients(ipu_channel_t channel, int32_t param[][3]);
923
924 /* SDC API */
925 int32_t ipu_sdc_init_panel(ipu_panel_t panel,
926                            uint32_t pixel_clk,
927                            uint16_t width, uint16_t height,
928                            uint32_t pixel_fmt,
929                            uint16_t hStartWidth, uint16_t hSyncWidth,
930                            uint16_t hEndWidth, uint16_t vStartWidth,
931                            uint16_t vSyncWidth, uint16_t vEndWidth,
932                            ipu_di_signal_cfg_t sig);
933
934 int32_t ipu_sdc_set_global_alpha(bool enable, uint8_t alpha);
935 int32_t ipu_sdc_set_color_key(ipu_channel_t channel, bool enable,
936                               uint32_t colorKey);
937 int32_t ipu_sdc_set_brightness(uint8_t value);
938
939 int32_t ipu_init_sync_panel(int disp,
940                             uint32_t pixel_clk,
941                             uint16_t width, uint16_t height,
942                             uint32_t pixel_fmt,
943                             uint16_t h_start_width, uint16_t h_sync_width,
944                             uint16_t h_end_width, uint16_t v_start_width,
945                             uint16_t v_sync_width, uint16_t v_end_width,
946                             uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
947
948 int32_t ipu_disp_set_window_pos(ipu_channel_t channel, int16_t x_pos,
949                                 int16_t y_pos);
950 int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, bool enable,
951                                   uint8_t alpha);
952 int32_t ipu_disp_set_color_key(ipu_channel_t channel, bool enable,
953                                uint32_t colorKey);
954 int32_t ipu_disp_set_gamma_correction(ipu_channel_t channel, bool enable,
955                                 int constk[], int slopek[]);
956
957 int ipu_init_async_panel(int disp, int type, uint32_t cycle_time,
958                          uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
959 void ipu_disp_direct_write(ipu_channel_t channel, u32 value, u32 offset);
960 void ipu_reset_disp_panel(void);
961
962 /* ADC API */
963 int32_t ipu_adc_write_template(display_port_t disp, uint32_t * pCmd,
964                                bool write);
965
966 int32_t ipu_adc_set_update_mode(ipu_channel_t channel,
967                                 ipu_adc_update_mode_t mode,
968                                 uint32_t refresh_rate, unsigned long addr,
969                                 uint32_t * size);
970
971 int32_t ipu_adc_get_snooping_status(uint32_t * statl, uint32_t * stath);
972
973 int32_t ipu_adc_write_cmd(display_port_t disp, cmddata_t type,
974                           uint32_t cmd, const uint32_t * params,
975                           uint16_t numParams);
976
977 int32_t ipu_adc_init_panel(display_port_t disp,
978                            uint16_t width, uint16_t height,
979                            uint32_t pixel_fmt,
980                            uint32_t stride,
981                            ipu_adc_sig_cfg_t sig,
982                            display_addressing_t addr,
983                            uint32_t vsync_width, vsync_t mode);
984
985 int32_t ipu_adc_init_ifc_timing(display_port_t disp, bool read,
986                                 uint32_t cycle_time,
987                                 uint32_t up_time,
988                                 uint32_t down_time,
989                                 uint32_t read_latch_time, uint32_t pixel_clk);
990
991 /* CMOS Sensor Interface API */
992 int32_t ipu_csi_init_interface(uint16_t width, uint16_t height,
993                                uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
994
995 int32_t ipu_csi_enable_mclk(int src, bool flag, bool wait);
996
997 static inline int32_t ipu_csi_enable_mclk_if(int src, uint32_t csi,
998                 bool flag, bool wait)
999 {
1000 #ifdef CONFIG_MXC_IPU_V1
1001         return ipu_csi_enable_mclk(src, flag, wait);
1002 #else
1003         return ipu_csi_enable_mclk(csi, flag, wait);
1004 #endif
1005 }
1006
1007 int ipu_csi_read_mclk_flag(void);
1008
1009 void ipu_csi_flash_strobe(bool flag);
1010
1011 void ipu_csi_get_window_size(uint32_t *width, uint32_t *height, uint32_t csi);
1012
1013 void ipu_csi_set_window_size(uint32_t width, uint32_t height, uint32_t csi);
1014
1015 void ipu_csi_set_window_pos(uint32_t left, uint32_t top, uint32_t csi);
1016
1017 /* Post Filter functions */
1018 int32_t ipu_pf_set_pause_row(uint32_t pause_row);
1019
1020 uint32_t bytes_per_pixel(uint32_t fmt);
1021
1022 /* New added for IPU-lib functionality*/
1023 int ipu_open(void);
1024 int ipu_register_generic_isr(int irq, void *dev);
1025 void ipu_close(void);
1026
1027 /* two stripe calculations */
1028 struct stripe_param{
1029         unsigned int input_width; /* width of the input stripe */
1030         unsigned int output_width; /* width of the output stripe */
1031         unsigned int input_column; /* the first column on the input stripe */
1032         unsigned int output_column; /* the first column on the output stripe */
1033         unsigned int idr;
1034         /* inverse downisizing ratio parameter; expressed as a power of 2 */
1035         unsigned int irr;
1036         /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
1037 };
1038
1039 typedef struct _ipu_stripe_parm {
1040         unsigned int input_width;
1041         unsigned int output_width;
1042         unsigned int maximal_stripe_width;
1043         unsigned long long cirr;
1044         unsigned int equal_stripes;
1045         u32 input_pixelformat;
1046         u32 output_pixelformat;
1047         struct stripe_param left;
1048         struct stripe_param right;
1049 } ipu_stripe_parm;
1050
1051 typedef struct _ipu_channel_parm {
1052         ipu_channel_t channel;
1053         ipu_channel_params_t params;
1054         bool flag;
1055 } ipu_channel_parm;
1056
1057 typedef struct _ipu_channel_buf_parm {
1058         ipu_channel_t channel;
1059         ipu_buffer_t type;
1060         uint32_t pixel_fmt;
1061         uint16_t width;
1062         uint16_t height;
1063         uint16_t stride;
1064         ipu_rotate_mode_t rot_mode;
1065         dma_addr_t phyaddr_0;
1066         dma_addr_t phyaddr_1;
1067         uint32_t u_offset;
1068         uint32_t v_offset;
1069         uint32_t bufNum;
1070 } ipu_channel_buf_parm;
1071
1072 typedef struct _ipu_buf_offset_parm {
1073         ipu_channel_t channel;
1074         ipu_buffer_t type;
1075         uint32_t pixel_fmt;
1076         uint16_t width;
1077         uint16_t height;
1078         uint16_t stride;
1079         uint32_t u_offset;
1080         uint32_t v_offset;
1081         uint32_t vertical_offset;
1082         uint32_t horizontal_offset;
1083 } ipu_buf_offset_parm;
1084
1085 typedef struct _ipu_channel_link {
1086         ipu_channel_t src_ch;
1087         ipu_channel_t dest_ch;
1088 } ipu_channel_link;
1089
1090 typedef struct _ipu_channel_info {
1091         ipu_channel_t channel;
1092         bool stop;
1093 } ipu_channel_info;
1094
1095 typedef struct ipu_irq_info {
1096         uint32_t irq;
1097          irqreturn_t(*handler) (int, void *);
1098         uint32_t irq_flags;
1099         char *devname;
1100         void *dev_id;
1101 } ipu_irq_info;
1102
1103 typedef struct _ipu_sdc_panel_info {
1104         ipu_panel_t panel;
1105         uint32_t pixel_clk;
1106         uint16_t width;
1107         uint16_t height;
1108         uint32_t pixel_fmt;
1109         uint16_t hStartWidth;
1110         uint16_t hSyncWidth;
1111         uint16_t hEndWidth;
1112         uint16_t vStartWidth;
1113         uint16_t vSyncWidth;
1114         uint16_t vEndWidth;
1115         ipu_di_signal_cfg_t signal;
1116 } ipu_sdc_panel_info;
1117
1118 typedef struct _ipu_sdc_window_pos {
1119         ipu_channel_t channel;
1120         int16_t x_pos;
1121         int16_t y_pos;
1122 } ipu_sdc_window_pos;
1123
1124 typedef struct _ipu_sdc_global_alpha {
1125         bool enable;
1126         uint8_t alpha;
1127 } ipu_sdc_global_alpha;
1128
1129 typedef struct _ipu_sdc_color_key {
1130         ipu_channel_t channel;
1131         bool enable;
1132         uint32_t colorKey;
1133 } ipu_sdc_color_key;
1134
1135 typedef struct _ipu_adc_template {
1136         display_port_t disp;
1137         uint32_t *pCmd;
1138         bool write;
1139 } ipu_adc_template;
1140
1141 typedef struct _ipu_adc_update {
1142         ipu_channel_t channel;
1143         ipu_adc_update_mode_t mode;
1144         uint32_t refresh_rate;
1145         unsigned long addr;
1146         uint32_t *size;
1147 } ipu_adc_update;
1148
1149 typedef struct _ipu_adc_snoop {
1150         uint32_t *statl;
1151         uint32_t *stath;
1152 } ipu_adc_snoop;
1153
1154 typedef struct _ipu_adc_cmd {
1155         display_port_t disp;
1156         cmddata_t type;
1157         uint32_t cmd;
1158         uint32_t *params;
1159         uint16_t numParams;
1160 } ipu_adc_cmd;
1161
1162 typedef struct _ipu_adc_panel {
1163         display_port_t disp;
1164         uint16_t width;
1165         uint16_t height;
1166         uint32_t pixel_fmt;
1167         uint32_t stride;
1168         ipu_adc_sig_cfg_t signal;
1169         display_addressing_t addr;
1170         uint32_t vsync_width;
1171         vsync_t mode;
1172 } ipu_adc_panel;
1173
1174 typedef struct _ipu_adc_ifc_timing {
1175         display_port_t disp;
1176         bool read;
1177         uint32_t cycle_time;
1178         uint32_t up_time;
1179         uint32_t down_time;
1180         uint32_t read_latch_time;
1181         uint32_t pixel_clk;
1182 } ipu_adc_ifc_timing;
1183
1184 typedef struct _ipu_csi_interface {
1185         uint16_t width;
1186         uint16_t height;
1187         uint16_t pixel_fmt;
1188         ipu_csi_signal_cfg_t signal;
1189 } ipu_csi_interface;
1190
1191 typedef struct _ipu_csi_mclk {
1192         int src;
1193         bool flag;
1194         bool wait;
1195 } ipu_csi_mclk;
1196
1197 typedef struct _ipu_csi_window {
1198         uint32_t left;
1199         uint32_t top;
1200 } ipu_csi_window;
1201
1202 typedef struct _ipu_csi_window_size {
1203         uint32_t width;
1204         uint32_t height;
1205 } ipu_csi_window_size;
1206
1207 typedef struct _ipu_event_info {
1208         int irq;
1209         void *dev;
1210 } ipu_event_info;
1211
1212 typedef struct _ipu_mem_info {
1213         dma_addr_t paddr;
1214         void *vaddr;
1215         int size;
1216 } ipu_mem_info;
1217
1218 typedef struct _ipu_csc_update {
1219         ipu_channel_t channel;
1220         int **param;
1221 } ipu_csc_update;
1222
1223 /* IOCTL commands */
1224
1225 #define IPU_INIT_CHANNEL              _IOW('I',0x1,ipu_channel_parm)
1226 #define IPU_UNINIT_CHANNEL            _IOW('I',0x2,ipu_channel_t)
1227 #define IPU_INIT_CHANNEL_BUFFER       _IOW('I',0x3,ipu_channel_buf_parm)
1228 #define IPU_UPDATE_CHANNEL_BUFFER     _IOW('I',0x4,ipu_channel_buf_parm)
1229 #define IPU_SELECT_CHANNEL_BUFFER     _IOW('I',0x5,ipu_channel_buf_parm)
1230 #define IPU_LINK_CHANNELS             _IOW('I',0x6,ipu_channel_link)
1231 #define IPU_UNLINK_CHANNELS           _IOW('I',0x7,ipu_channel_link)
1232 #define IPU_ENABLE_CHANNEL            _IOW('I',0x8,ipu_channel_t)
1233 #define IPU_DISABLE_CHANNEL           _IOW('I',0x9,ipu_channel_info)
1234 #define IPU_ENABLE_IRQ                _IOW('I',0xA,int)
1235 #define IPU_DISABLE_IRQ               _IOW('I',0xB,int)
1236 #define IPU_CLEAR_IRQ                 _IOW('I',0xC,int)
1237 #define IPU_FREE_IRQ                  _IOW('I',0xD,ipu_irq_info)
1238 #define IPU_REQUEST_IRQ_STATUS        _IOW('I',0xE,int)
1239 #define IPU_SDC_INIT_PANEL            _IOW('I',0xF,ipu_sdc_panel_info)
1240 #define IPU_SDC_SET_WIN_POS           _IOW('I',0x10,ipu_sdc_window_pos)
1241 #define IPU_SDC_SET_GLOBAL_ALPHA      _IOW('I',0x11,ipu_sdc_global_alpha)
1242 #define IPU_SDC_SET_COLOR_KEY         _IOW('I',0x12,ipu_sdc_color_key)
1243 #define IPU_SDC_SET_BRIGHTNESS        _IOW('I',0x13,int)
1244 #define IPU_ADC_WRITE_TEMPLATE        _IOW('I',0x14,ipu_adc_template)
1245 #define IPU_ADC_UPDATE                _IOW('I',0x15,ipu_adc_update)
1246 #define IPU_ADC_SNOOP                 _IOW('I',0x16,ipu_adc_snoop)
1247 #define IPU_ADC_CMD                   _IOW('I',0x17,ipu_adc_cmd)
1248 #define IPU_ADC_INIT_PANEL            _IOW('I',0x18,ipu_adc_panel)
1249 #define IPU_ADC_IFC_TIMING            _IOW('I',0x19,ipu_adc_ifc_timing)
1250 #define IPU_CSI_INIT_INTERFACE        _IOW('I',0x1A,ipu_csi_interface)
1251 #define IPU_CSI_ENABLE_MCLK           _IOW('I',0x1B,ipu_csi_mclk)
1252 #define IPU_CSI_READ_MCLK_FLAG        _IOR('I',0x1C,ipu_csi_mclk)
1253 #define IPU_CSI_FLASH_STROBE          _IOW('I',0x1D,ipu_csi_mclk)
1254 #define IPU_CSI_GET_WIN_SIZE          _IOR('I',0x1E,ipu_csi_window_size)
1255 #define IPU_CSI_SET_WIN_SIZE          _IOW('I',0x1F,ipu_csi_window_size)
1256 #define IPU_CSI_SET_WINDOW            _IOW('I',0x20,ipu_csi_window)
1257 #define IPU_PF_SET_PAUSE_ROW          _IOW('I',0x21, uint32_t)
1258 #define IPU_REGISTER_GENERIC_ISR      _IOW('I', 0x22, ipu_event_info)
1259 #define IPU_GET_EVENT                 _IOWR('I', 0x23, ipu_event_info)
1260 #define IPU_ALOC_MEM                  _IOWR('I', 0x24, ipu_mem_info)
1261 #define IPU_FREE_MEM                  _IOW('I', 0x25, ipu_mem_info)
1262 #define IPU_IS_CHAN_BUSY              _IOW('I', 0x26, ipu_channel_t)
1263 #define IPU_CALC_STRIPES_SIZE         _IOWR('I', 0x27, ipu_stripe_parm)
1264 #define IPU_UPDATE_BUF_OFFSET         _IOW('I', 0x28, ipu_buf_offset_parm)
1265 #define IPU_CSC_UPDATE                _IOW('I', 0x29, ipu_csc_update)
1266
1267 int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
1268                                 unsigned int output_frame_width,
1269                                 const unsigned int maximal_stripe_width,
1270                                 const unsigned long long cirr,
1271                                 const unsigned int equal_stripes,
1272                                 u32 input_pixelformat,
1273                                 u32 output_pixelformat,
1274                                 struct stripe_param *left,
1275                                 struct stripe_param *right);
1276 #endif