intel/gm45: Fix interpretation of VT-d disable bit
authorNico Huber <nico.huber@secunet.com>
Tue, 14 May 2013 09:02:43 +0000 (11:02 +0200)
committerStefan Reinauer <stefan.reinauer@coreboot.org>
Wed, 22 May 2013 15:59:10 +0000 (17:59 +0200)
commit0da92863a754828eb807f1a15927f0dc288a1788
tree65d6c31ee5f7989fd82633c3743e5d8c8f525c42
parent0f43af2ebb0d34ef6106d39d8614590253d5f4a9
intel/gm45: Fix interpretation of VT-d disable bit

When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
src/northbridge/intel/gm45/igd.c