gnutoo-for-coreboot:coreboot.git
4 years agoAllow mainboard vendor name and part number override in SMBIOS tables
Peter Stuge [Thu, 4 Oct 2012 19:18:13 +0000 (21:18 +0200)]
Allow mainboard vendor name and part number override in SMBIOS tables

Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b
Signed-off-by: Peter Stuge <peter@stuge.se>
4 years agousbdebug: Fix use without EARLY_CONSOLE
Kyösti Mälkki [Thu, 6 Jun 2013 07:29:49 +0000 (10:29 +0300)]
usbdebug: Fix use without EARLY_CONSOLE

If EARLY_CONSOLE is not selected, the PCI function for EHCI
host controller must be configured in ramstage instead.

Change-Id: I20f7569f79484c744bc413450bfa139052f3580f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
4 years agoLenovo X60: Add int15 handler
Denis 'GNUtoo' Carikli [Tue, 21 May 2013 01:13:46 +0000 (03:13 +0200)]
Lenovo X60: Add int15 handler

Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL,
  The VGA option rom doesn't init the right display:
  it initializes the external display, where we have
  a black scren(with backlight on).

This commit is based on the code of mainboard.c in
  src/mainboard/roda/rk886ex.

Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
4 years agoi945: Add Display defines for int15h handler.
Denis 'GNUtoo' Carikli [Sun, 26 May 2013 21:56:43 +0000 (23:56 +0200)]
i945: Add Display defines for int15h handler.

Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3306
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoqemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpi
Gerd Hoffmann [Thu, 30 May 2013 08:58:06 +0000 (10:58 +0200)]
qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpi

First copy over from SeaBIOS git repo, then adapt for coreboot:

Disable cpu/pci hotplug bits.  Disable dynamic pci window.
Both depend on stuff in the SSDT tables created by SeaBIOS.

Bits are left in, but deactivated via #if 0, so it's easier
to see the differences when diffing the coreboot tables with
the SeaBIOS tables.

Adapt dsdt DefinitionBlock.

Enable acpi table generation in acpi_tables.c.

With this patch linux boots successfully with ACPI enabled.
It's not bug-free though.  Missing cpu detection leads to
funky messages like this one:

  weird, boot CPU (#0) not listed by the BIOS.

and SMP most likely wouldn't work either.

Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3342
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
4 years agoec/acpi: Add ACPI methods for generic EC access
Nico Huber [Thu, 23 May 2013 14:35:05 +0000 (16:35 +0200)]
ec/acpi: Add ACPI methods for generic EC access

Port most of the functions found in ec/acpi/ec.c to ACPI Source Language
(ASL). These functions are used to control embedded controllers with the
standard ACPI interface (mostly through i/o ports 0x62 / 0x66).

The following methods are implemented and tested against the power
managements channels of a ITE IT8516E embedded controller:
 * WAIT_EC_SC           Wait for a bit in the EC_SC register
 * SEND_EC_COMMAND      Send one command byte to the EC_SC register
 * SEND_EC_DATA         Send one data byte to the EC_DATA register
 * RECV_EC_DATA         Read one byte of data from the EC_DATA register
 * EC_READ              Read one byte from ec memory (through cmd 0x80)
 * EC_WRITE             Write one byte to ec memory (through cmd 0x81)

To use the provided methods, one should include `ec/acpi/ec.asl` in the
EC device code. Prior doing so, two macros should be defined to identify
the used i/o ports:
 * EC_SC_IO     I/o address of the EC_SC register
 * EC_DATA_IO   I/o address of the EC_DATA register

Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3285
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
4 years agoIntel Atom cpu support to msrtool
Olivier Langlois [Mon, 3 Jun 2013 05:30:25 +0000 (01:30 -0400)]
Intel Atom cpu support to msrtool

Added support for Intel Atom cpu to msrtool
Fixed a cut&paste error in nehalem msr bits definition

It has been tested with a N455 cpu and msrtool output can be review at:
http://www.trillion01.com/coreboot/msrtool_atom.txt

Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Reviewed-on: http://review.coreboot.org/3351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoAMD Trinity: Remove unnecessary lookup table copy
Bruce Griffith [Tue, 4 Jun 2013 20:22:25 +0000 (14:22 -0600)]
AMD Trinity: Remove unnecessary lookup table copy

The DDI connector table and the PCIe Port List lookup table are
copied onto HEAP.  This copy is not needed since these are lookup
tables used to define the platform configuration.

Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoAGESA: Add "const" modifier to function parameters
Bruce Griffith [Tue, 4 Jun 2013 20:16:24 +0000 (14:16 -0600)]
AGESA: Add "const" modifier to function parameters

Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA.  This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.

Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoqemu: wind up new cpu chip
Gerd Hoffmann [Fri, 31 May 2013 07:26:55 +0000 (09:26 +0200)]
qemu: wind up new cpu chip

Add boot cpu to the device tree.  Figure the number of CPUs installed
(using the qemu firmware config interface) and add cpu devices for them,
so they show up in all generated BIOS tables correctly.  This gets SMP
going.

Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoqemu: add x86 cpu
Gerd Hoffmann [Fri, 31 May 2013 07:23:26 +0000 (09:23 +0200)]
qemu: add x86 cpu

This patch adds a qemu x86 cpu chip.  It has no initialization function
as this isn't needed on virtual hardware.  A virtual machine can have
pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu
-cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu
which is (almost) identical to the one on the host machine.  So I've
added X86_VENDOR_ANY as wildcard match for the cpu_table.

Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoec/kontron/it8516e: Add it8516e EC driver
Nico Huber [Thu, 2 May 2013 13:26:08 +0000 (15:26 +0200)]
ec/kontron/it8516e: Add it8516e EC driver

This driver communicates with the IT8516e on the Kontron KTQM77.
Since we don't know if the firmware and protocol are standard for
the chip or customized to the board, call it kontron/it8516e.

Change-Id: I7382172c6d865d60106c929124444821a07a5184
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/bd82x6x: Add option to include ethernet firmware
Nico Huber [Tue, 14 May 2013 13:14:08 +0000 (15:14 +0200)]
intel/bd82x6x: Add option to include ethernet firmware

Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/bd82x6x: fix building usb debug on SNB/IVB
Patrick Georgi [Thu, 2 May 2013 09:44:02 +0000 (11:44 +0200)]
intel/bd82x6x: fix building usb debug on SNB/IVB

Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3389
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years ago(Trivial) early_smbus: fix printsmbus macro
Alexandru Gagniuc [Thu, 6 Jun 2013 01:01:42 +0000 (20:01 -0500)]
(Trivial) early_smbus: fix printsmbus macro

When I've first written this macro in 2011, the correct define for
verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since
been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made
the printsmbus macro always evaluate to an empty statement.

Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus
functional again.

Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3379
Tested-by: build bot (Jenkins)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
4 years agoqemu: add power management function to device tree
Gerd Hoffmann [Fri, 31 May 2013 11:39:24 +0000 (13:39 +0200)]
qemu: add power management function to device tree

Needed to make 'register "gpo" = ...' work.
While being at it add comments saying which device is which.

Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3346
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoconsole: log qemu debugcon detection result
Gerd Hoffmann [Thu, 30 May 2013 11:23:38 +0000 (13:23 +0200)]
console: log qemu debugcon detection result

Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoconsole: add qemu debugcon detection
Gerd Hoffmann [Thu, 30 May 2013 08:33:38 +0000 (10:33 +0200)]
console: add qemu debugcon detection

The qemu debugcon port returns 0xe9 on reads in case the device is
present.  Use that for detection and write console output to the
port only in case the device is actually present.

Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoconsole: add qemu prefix to debugcon
Gerd Hoffmann [Thu, 30 May 2013 08:32:31 +0000 (10:32 +0200)]
console: add qemu prefix to debugcon

Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoqemu: Initial support for the qemu firmware config interface.
Gerd Hoffmann [Thu, 30 May 2013 13:41:48 +0000 (15:41 +0200)]
qemu: Initial support for the qemu firmware config interface.

qemu has a special device to pass configuration information
from qemu to the firmware.  This patch adds initial support
the interface, namely some infrastructure, detection code and
a function to query the number of CPUs.

Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoRevert "Asus F2A85-M: Activate IOMMU support"
Paul Menzel [Wed, 5 Jun 2013 06:34:20 +0000 (08:34 +0200)]
Revert "Asus F2A85-M: Activate IOMMU support"

This reverts commit eed28f97b375a9469a2872996c19eb102647052e.

For whatever reason, the dependencies were lost in Gerrit and the
commit [1] was submitted without its dependencies. As a result
buidling the ASUS F2A85-M fails now [2] and therefore commits
based on this commit fail to pass the buid tests by Jenkins.

    […]
    Created CBFS image (capacity = 8387656 bytes)
        LINK       cbfs/fallback/romstage_null.debug
        CC         cbfs/fallback/coreboot_ram.debug
    coreboot-builds/asus_f2a85-m/generated/coreboot_ram.o:(.data+0x16b9c): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/coreboot_ram.debug] Error 1
    make: *** Waiting for unfinished jobs....
    coreboot-builds/asus_f2a85-m/mainboard/asus/f2a85-m/buildOpts.romstage.o:(.data+0x3d8): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
    […]

Therefore revert the commit to get the tree working again and
submit this patch with its dependencies again.

[1] http://review.coreboot.org/#/c/3317/
[2] http://qa.coreboot.org/job/coreboot-gerrit/6618/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I911755884da09eb0a0651b8db07ee2a32e6eaaaa
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
4 years agoqemu: fix IRQ routing setup
Gerd Hoffmann [Wed, 29 May 2013 12:59:36 +0000 (14:59 +0200)]
qemu: fix IRQ routing setup

Do the setup for all PCI slots, not only the third.

Also remove the bogus message, as slot 3 may carry
any device, not only NICs.

This makes IRQ setup simliar to SeaBIOS.

SeaBIOS assignments (with patch for logging added,
and a bunch of pci devices for testing purposes):

    PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
    PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
    PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
    PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11

Coreboot assignments without this patch:

    Assigning IRQ 11 to 0:3.0

Coreboot assignments with this patch:

    Assigning IRQ 10 to 0:1.3
    Assigning IRQ 11 to 0:3.0
    Assigning IRQ 11 to 0:4.0
    Assigning IRQ 10 to 0:5.0
    Assigning IRQ 10 to 0:6.0
    Assigning IRQ 10 to 0:1d.0
    Assigning IRQ 10 to 0:1d.1
    Assigning IRQ 11 to 0:1d.2
    Assigning IRQ 11 to 0:1d.7

Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
4 years agoIntel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS
Denis 'GNUtoo' Carikli [Tue, 4 Jun 2013 02:48:11 +0000 (04:48 +0200)]
Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS

X86EMU_DEBUG_TIMING is needed for producing i915tool
  compatible output. So add its dependencies to the
  i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS,
  which depends on HAVE_MONOTONIC_TIMER which
  LAPIC_MONOTONIC_TIMER provides/selects.

Note that UDELAY_LAPIC is already selected by the Intel CPU.

Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3356
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAsus F2A85-M: Activate IOMMU support
Rudolf Marek [Mon, 27 May 2013 14:12:00 +0000 (16:12 +0200)]
Asus F2A85-M: Activate IOMMU support

Activate the IOMMU support for the Asus F2A85-M.

Add the device to `devicetree.cb`.

    $ pci -s 0.2
    […]
    00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit

    $ dmesg
    […]
    [    0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02  AMD   AMDIOMMU 00000001 AMD  00000000)
    [    0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02    AMD     ALIB 00000001 MSFT 04000000)
    [    0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD    POWERNOW 00000001 AMD  00000001)
    [    0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE   COREBOOT 0000002A CORE 0000002A)
    […]
    [    0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS
    […]
    [    0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000
    [    0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600
    [    0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000
    […]
    [    0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
    [    0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT]
    [    0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT]
    [    0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT]
    [    0.598073]  pci0000:00: >Requesting ACPI _OSC control (0x1d)
    [    0.603808]  pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d
    [    0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM
    [    0.620508] Freeing initrd memory: 14876k freed
    […]
    [    0.882674] pci 0000:00:01.0: >Boot video device
    [    0.882876] PCI: CLS 64 bytes, default 64
    [    0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features:  PreF PPR GT IA
    [    0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X
    [    0.917457] AMD-Vi: Lazy IO/TLB flushing enabled
    [    0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
    [    0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff]
    [    0.938535] LVT offset 0 assigned for vector 0x400
    [    0.943338] perf: AMD IBS detected (0x000000ff)
    [    0.948037] audit: initializing netlink socket (disabled)
    [    0.953432] type=2000 audit(1369659616.800:1): initialized
    [    0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages
    […]
    [    7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used)
    [    7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
    […]
    [    7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X
    [    7.885525] radeon 0000:00:01.0: >radeon: using MSI.
    […]
    [    8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010]
    [    8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010]
    [    8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010]
    [    8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010]
    [    8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010]
    [    8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010]
    [    8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010]
    [    8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010]
    [    8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010]
    [    8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010]
    [    8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010]
    [    8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010]
    [    8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010]
    [    8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010]
    [    8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010]
    [    8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010]
    [    8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010]
    [    8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010]
    [    8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010]
    [    8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010]
    [    8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010]
    [    8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010]
    [    8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010]
    [    8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010]
    [    8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010]
    [    8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010]
    [    8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010]
    [    8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010]
    [    8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010]
    [    8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010]
    [    8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010]
    […]
    [    8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010]
    [    8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010]
    [    8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010]
    [    8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010]
    [    8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010]
    [    8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010]
    [    8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010]
    [    8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010]
    [    8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010]
    [    8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010]
    [    8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010]
    [    8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010]
    [    8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010]
    [    8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010]
    [    8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010]
    [    8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010]
    [    8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010]
    [    8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010]
    [    8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010]
    [    8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010]
    [    8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010]
    [    8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010]
    [    8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010]
    [    8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010]
    [    8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010]
    [    8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010]
    [    8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010]
    [    8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010]
    [    8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010]
    [    8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010]
    [    8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010]
    [    8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010]
    [    8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010]
    [    8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
    [    8.963165] radeon 0000:00:01.0: >WB enabled
    […]

It is not known, what the implications of the `IO_PAGE_FAULT` are.

Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoYabel : Add tracing option needed by i915tool.
Denis 'GNUtoo' Carikli [Tue, 14 May 2013 22:19:49 +0000 (00:19 +0200)]
Yabel : Add tracing option needed by i915tool.

This patch was made by listenning to what Ron Minnich told
  me to do on #coreboot IRC channel on Freenode with my
  adaptations on top.

i915tool is at https://code.google.com/p/i915tool/ ,
  the one in coreboot is outdated.

Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoviatool: Add utility to read various configuration bits on VIA systems
Alexandru Gagniuc [Fri, 10 Aug 2012 08:55:42 +0000 (03:55 -0500)]
viatool: Add utility to read various configuration bits on VIA systems

viatool is a utility for extracting useful for extracting certain configuration
bits on VIA chipsets and CPUs. It is a fork of inteltool.

viatool is currently focused on "quirks". Quirks are device configurations that
cannot be accessed directly. They are implemented as hierarchical configurations
in the PCI or memory address spaces (index/data register pairs). Such
configurations refer to hardware parameters that are board specific. Those
parameters would otherwise be difficult to extract from a system running the
vendor's firmware.

viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are
nearly identical.

Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1430
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoMove the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
Ronald G. Minnich [Fri, 31 May 2013 17:36:52 +0000 (19:36 +0200)]
Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture

The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
since it was defined in sandybridge. It is really
more of an x86 thing however, and we now have
three systems that can use it.

I considered making this more general, since it technically
can apply to PTE-based systems like ARM, and maybe we should.
But the 'WRCOMB' moniker is usually closely tied to the x86.

Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3349
Tested-by: build bot (Jenkins)
4 years agoLenovo X60: Add CMOS defaults.
Denis 'GNUtoo' Carikli [Wed, 29 May 2013 19:25:05 +0000 (21:25 +0200)]
Lenovo X60: Add CMOS defaults.

After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
     # ./nvramtool -a
     boot_option = Fallback
     last_boot = Fallback
     baud_rate = 115200
     debug_level = Spew
     hyper_threading = Enable
     nmi = Enable
     boot_devices = ''
     boot_default = 0x40
     cmos_defaults_loaded = Yes
     lpt = Enable
     volume = 0xff
     tft_brightness = 0xbf
     first_battery = Primary
     bluetooth = Enable

The code for handling the invalid CMOS space in mainboard.c
  is now useless and so it was removed.

Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3335
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoAsus M4A785T-M: Add CMOS defaults.
Denis 'GNUtoo' Carikli [Thu, 9 May 2013 14:14:59 +0000 (16:14 +0200)]
Asus M4A785T-M: Add CMOS defaults.

After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Enable
    baud_rate = 115200
    hw_scrubber = Enable
    interleave_chip_selects = Enable
    max_mem_clock = 400Mhz
    multi_core = Enable
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0xc
    slow_cpu = off
    nmi = Enable
    iommu = Enable
    nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoPC Engines ALIX.1C: Add CMOS defaults.
Denis 'GNUtoo' Carikli [Thu, 9 May 2013 21:35:18 +0000 (23:35 +0200)]
PC Engines ALIX.1C: Add CMOS defaults.

After Booting the BIOS, flashing coreboot
  and booting coreboot with that patch we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Disable
    baud_rate = 115200
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0x7f
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3323
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agopci_ids.h: Add PCI IDs for VIA VX900 chipset
Alexandru Gagniuc [Tue, 21 May 2013 19:50:19 +0000 (14:50 -0500)]
pci_ids.h: Add PCI IDs for VIA VX900 chipset

Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3268
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
4 years agosuperiotool: Add dump facility for HWM of W83627DHG-P
Nico Huber [Thu, 25 Apr 2013 13:00:15 +0000 (15:00 +0200)]
superiotool: Add dump facility for HWM of W83627DHG-P

Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agosuperiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f
Nico Huber [Thu, 25 Apr 2013 13:10:46 +0000 (15:10 +0200)]
superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f

Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3359
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agolibpayload: Whitelist Mobile Panther Point AHCI controller
Nico Huber [Tue, 21 May 2013 10:26:47 +0000 (12:26 +0200)]
libpayload: Whitelist Mobile Panther Point AHCI controller

Add the Mobile Panther Point (PPT) AHCI controller (DEVID 0x1e03) to
the list of tested controllers. Also comment the only other listed
controller (Mobile ICH9).

The PPT AHCI controller was tested with a QM77 chipset on a Kontron
KTQM77 board.

Change-Id: Ia396761411f4f9289af11ec8e1b144512b2fc126
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agofix tinycurses
Patrick Georgi [Tue, 28 May 2013 11:56:54 +0000 (13:56 +0200)]
fix tinycurses

Change-Id: I9e7bde7b2c90b8b34c6aa8e90a16cd29dc108fe9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3360
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agocoreboot: Add generic early SMBus API
Alexandru Gagniuc [Tue, 21 May 2013 17:17:58 +0000 (12:17 -0500)]
coreboot: Add generic early SMBus API

Early SMBUS code with similar functionality is duplicated for all
southbridges. Add a generic SMBus API (function declarations) designed to
unify the early SMBus structure.

This patch only adds the API. It does not implement any hardware-specific
bits.

Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/143
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoDDR3: Add utilities for creating MRS commands
Alexandru Gagniuc [Mon, 3 Jun 2013 18:58:10 +0000 (13:58 -0500)]
DDR3: Add utilities for creating MRS commands

MRS commands are used to tell the DRAM chip what timing and what
termination and drive strength to use, along with other parameters.
The MRS commands are defined by the DDR3 specification [1]. This
makes MRS commands hardware-independent.

MRS command creation is duplicated in various shapes and forms in any
chipset that does DDR3. This is an effort to create a generic MRS API
that can be used with any chipset.

This is used in the VX900 branch.

[1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf

Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoVIA Nano: Add microcode updates files
Alexandru Gagniuc [Tue, 4 Jun 2013 04:16:50 +0000 (23:16 -0500)]
VIA Nano: Add microcode updates files

While we had support for updating microcode on the VIA Nano CPUs for a
while now, we never included the actual microcode. Unlike, Intel and
AMD CPUs, VIA microcode is not available for download, and was
extracted from the vendor BIOS. It was not included in coreboot since
we never had explicit permission to do so. I have just received
confirmation from VIA that we can distribute the microcode.

Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3357
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
4 years agoAMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
Christian Gmeiner [Tue, 4 Jun 2013 15:40:40 +0000 (17:40 +0200)]
AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"

Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: convert spd_read_byte() to non-static version
Christian Gmeiner [Tue, 4 Jun 2013 15:34:35 +0000 (17:34 +0200)]
AMD Northbridge LX: convert spd_read_byte() to non-static version

Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"
Christian Gmeiner [Tue, 4 Jun 2013 15:27:22 +0000 (17:27 +0200)]
AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"

Move the include before static inline int spd_read_byte().

Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: rename get_systop() to get_top_of_ram()
Christian Gmeiner [Tue, 4 Jun 2013 14:23:43 +0000 (16:23 +0200)]
AMD Northbridge LX: rename get_systop() to get_top_of_ram()

Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3367
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: include northbridge.h in raminit.c
Christian Gmeiner [Tue, 4 Jun 2013 12:38:24 +0000 (14:38 +0200)]
AMD Northbridge LX: include northbridge.h in raminit.c

Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3365
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
Christian Gmeiner [Tue, 4 Jun 2013 12:30:50 +0000 (14:30 +0200)]
AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static

Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: add some missing includes
Christian Gmeiner [Tue, 4 Jun 2013 12:12:10 +0000 (14:12 +0200)]
AMD Northbridge LX: add some missing includes

This commit fixes problems if we build raminit.c
for romstage.

Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3363
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Northbridge LX: make sdram_* function prototypes non-static
Christian Gmeiner [Tue, 4 Jun 2013 12:08:46 +0000 (14:08 +0200)]
AMD Northbridge LX: make sdram_* function prototypes non-static

In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
line we need to do some prepartion steps. This commit is one of them.

Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3362
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Fam 15tn: Use all memory on systems with more than 4 GB
Siyuan Wang [Tue, 4 Jun 2013 11:56:22 +0000 (19:56 +0800)]
AMD Fam 15tn: Use all memory on systems with more than 4 GB

Take a Parmer board with 4G memory as an example.

Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.

When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is

    6: 0000000100000000 - 0000000118000000 = 1 RAM

This is not correct, it should be

    6: 0000000100000000 - 000000011f000000 = 1 RAM

This patch changes the memory layout when TOM2 is set.

Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agocrossgcc/buildgcc: Remove unneeded 'break' statements
David Hubbard [Tue, 28 May 2013 22:33:15 +0000 (16:33 -0600)]
crossgcc/buildgcc: Remove unneeded 'break' statements

Bash case statements are terminated with ';;'.

Unlike C, bash case statements will not continue to the next case. No 'break' is needed.

Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036
Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-on: http://review.coreboot.org/3330
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agodram: Add utilities for decoding DDR3 SPDs
Alexandru Gagniuc [Tue, 21 May 2013 19:43:45 +0000 (14:43 -0500)]
dram: Add utilities for decoding DDR3 SPDs

Add convenience utilities for decoding DDR3 SPDs and printing the
information to the console. These have proven invaluable when writing the
VX900 memory initialization.

These are used in the VX900 branch

Information printed has the following format:

> SPD Data for DIMM 51
>   Revision: 10
>   Type    : b
>   Key     : 2
>   Banks   : 8
>   Capacity: 1 Gb
>   Supported voltages: 1.5V
>   SDRAM width       : 8
>   Bus extension     : 0 bits
>   Bus width         : 64
>   Optional features : DLL-Off_mode RZQ/7 RZQ/6
>   Thermal features  : ASR ext_temp_range
>   Thermal sensor    : no
>   Standard SDRAM    : no
>   Row    addr bits  : 13
>   Column addr bits  : 10
>   Number of ranks   : 1
>   DIMM Capacity     : 1024 MB
>   CAS latencies     : 6 7 8 9
>   tCKmin            :   1.500 ns
>   tAAmin            :  13.125 ns
>   tWRmin            :  15.000 ns
>   tRCDmin           :  13.125 ns
>   tRRDmin           :   6.000 ns
>   tRPmin            :  13.125 ns
>   tRASmin           :  36.000 ns
>   tRCmin            :  49.125 ns
>   tRFCmin           : 110.000 ns
>   tWTRmin           :   7.500 ns
>   tRTPmin           :   7.500 ns
>   tFAWmin           :  30.000 ns

Change-Id: I30725a75caf74ac637db0a143344562bd9910466
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3267
Tested-by: build bot (Jenkins)
4 years agospd.h: Add all known SPD_MEMORY_TYPE definitions.
Alexandru Gagniuc [Tue, 21 May 2013 19:07:41 +0000 (14:07 -0500)]
spd.h: Add all known SPD_MEMORY_TYPE definitions.

This file was missing some definitions, so add them. Also turn the defines
into an enum. The reason for doing this is that functions can now
explicitly take an spd_memory_type as a parameter:

> int do_something_with_dram(enum spd_memory_type type, ...)

Which is a lot more explicit and readable than:

> int do_something_with_dram(u8 type, ...)

These are used in the VX900 branch.

Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3266
Tested-by: build bot (Jenkins)
4 years agoutil/cbmem: Fix format string in cbmem.c
Nico Huber [Sun, 26 May 2013 16:17:54 +0000 (18:17 +0200)]
util/cbmem: Fix format string in cbmem.c

Use PRIx64 to print a u64 instead of "llx". Fixes the following error:

cbmem.c: In function 'parse_cbtable':
cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=]

Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3301
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoinclude/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines
Paul Menzel [Mon, 13 May 2013 16:22:23 +0000 (18:22 +0200)]
include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other defines

Probably due to different (character) widths for a tab, sometimes only
one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For
the “correct” alignment, that means where a tab is eight characters,
two tabs are necessary. Change it accordingly.

Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3263
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoAsus F2A85-M: Fix the _CRS PCI0 bus info
Rudolf Marek [Mon, 27 May 2013 18:39:18 +0000 (20:39 +0200)]
Asus F2A85-M: Fix the _CRS PCI0 bus info

On Asus F2A85-M, the Linux kernel complains that the _CRS method does
not specify the number of PCI busses.

    [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS

Just put there 256. This should be part of re-factoring of the whole
ACPI stuff.

The same change was already done for the AMD Brazos (SB800) boards,
based on commit »Persimmon DSDT: Add secondary bus range to PCI0«
(4733c647) [1].

[1] http://review.coreboot.org/2592

Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3320
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
4 years agoAMD Geode CS5536: downgrade BIOS_ERR
Christian Gmeiner [Wed, 29 May 2013 20:30:18 +0000 (20:30 +0000)]
AMD Geode CS5536: downgrade BIOS_ERR

There is no need to use everywhere BIOS_ERR.

Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3307
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoconsole: add support for QEMU's debugcon
Gerd Hoffmann [Wed, 29 May 2013 11:06:22 +0000 (13:06 +0200)]
console: add support for QEMU's debugcon

Add support for sending debug output to an I/O port.

It can be used together with QEMU's isa-debugcon driver to log the
coreboot output to a file.  The port is configurable and defaults
to 0x402 which has established as the de facto standard. For example,
SeaBIOS+OVMF [1] use that one too.

[1] http://www.linux-kvm.org/page/OVMF
    Open Virtual Machine Firmware
Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agohaswell: allow for disabled hyperthreading
Aaron Durbin [Tue, 28 May 2013 19:26:29 +0000 (14:26 -0500)]
haswell: allow for disabled hyperthreading

There were assumptions being made in the haswell
MP and SMM code which assumed the APIC id space
was 1:1 w.r.t. cpu number. When hyperthreading is
disabled the APIC ids of the logical processors
are all even. That means the APIC id space is sparse.
Handle this situation.

Change-Id: Ibe79ab156c0a171208a77db8a252aa5b73205d6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agohaswell: fix overflow handling TOUUD
Aaron Durbin [Mon, 3 Jun 2013 14:46:56 +0000 (09:46 -0500)]
haswell: fix overflow handling TOUUD

It's possible that the TOUUD can be set to less than
4GiB. When that is the case the size_k variable is
an extremely large value. Instead ensure TOUUD is greater
than 4GiB before adding said resources.

Change-Id: I456633d6210824e60665281538300fd15656b86d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3352
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoIntel Lynx Point: LPC: Unify I/O APIC setup
Paul Menzel [Fri, 3 May 2013 10:17:02 +0000 (12:17 +0200)]
Intel Lynx Point: LPC: Unify I/O APIC setup

Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a412e6c41f48a86a79b72465f6cd81635
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194c712a40aa8444a530b2062876eabe3
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3182
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
4 years agoIntel BD82x6x: LPC: Unify I/O APIC setup
Paul Menzel [Fri, 3 May 2013 10:23:39 +0000 (12:23 +0200)]
Intel BD82x6x: LPC: Unify I/O APIC setup

Remove local copies of reading and writing I/O APIC registers by
using already available functions.

This change is similar to

    commit db4f875a412e6c41f48a86a79b72465f6cd81635
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Jan 31 17:24:12 2012 +0200

        IOAPIC: Divide setup_ioapic() in two parts.

        Reviewed-on: http://review.coreboot.org/300

and

    commit e614353194c712a40aa8444a530b2062876eabe3
    Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
    Date:   Tue Feb 26 17:24:41 2013 +0200

        Unify setting 82801a/b/c/d IOAPIC ID

        Reviewed-on: http://review.coreboot.org/2532

and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.

As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].

[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c

Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3183
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
4 years agonorthbridge/amd/amdmct: Use `static const` instead of `const static`
Paul Menzel [Sat, 4 May 2013 16:07:13 +0000 (18:07 +0200)]
northbridge/amd/amdmct: Use `static const` instead of `const static`

From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«

Found at <http://www.approxion.com/?p=41>.

The following command was used to make the change.

    $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'

As asked by Bruce Griffith, the changes in `src/vendorcode` were
reverted as that is what AMD prefers.

The same change was done already for AMD Persimmon in the following
commit.

    commit 824e192809e021b3cdee947a44b3a18d276bdb35
    Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Date:   Wed Feb 20 21:24:20 2013 +0100

        Persimmon: platform_cfg.h: Declare codec arrays as `static const`

        Reviewed-on: http://review.coreboot.org/2474

Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3197
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
4 years agoam335x: Clean up/fix some settings in the am335x Kconfig.
Gabe Black [Wed, 29 May 2013 14:42:20 +0000 (16:42 +0200)]
am335x: Clean up/fix some settings in the am335x Kconfig.

Some settings in the am335x Kconfig weren't actually used for anything, some
where place holders, and some where left over from another CPU. The memory
addresses are in the internal RAM in the SOC as described in the reference
manual. The stack is put where the internal ROM had its stack, and the
bootblock is put at the bottom of that region as the manual suggests. The
ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the
bootblock currently takes up.

Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3327
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
4 years agoProvide sane Kconfig default for cmos.default.
Denis 'GNUtoo' Carikli [Tue, 28 May 2013 11:46:12 +0000 (13:46 +0200)]
Provide sane Kconfig default for cmos.default.

Without that fix we have with CONFIG_USE_OPTION_TABLE:

    OPTION     cmos_layout.bin
  build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin
  make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'.  Stop.
  rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c

That log was captured with make V=1 but the error also appear with make.

Tested on the PC Engines ALIX.1C with the following commit (Change-Id: Ia87b090) [1]:

  PC Engines ALIX.1C: Add CMOS defaults.

[1] http://review.coreboot.org/#/c/3323/

Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3223
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
4 years agoLenovo ThinkPad X60: cleanup Native VGA init.
Denis 'GNUtoo' Carikli [Fri, 26 Apr 2013 12:49:27 +0000 (14:49 +0200)]
Lenovo ThinkPad X60: cleanup Native VGA init.

Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3272
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Trinity boards: Add reserved memory area for SPI base address in ACPI
Steven Sherk [Wed, 22 May 2013 19:49:18 +0000 (13:49 -0600)]
AMD Trinity boards: Add reserved memory area for SPI base address in ACPI

    - SPI controller base address gets overwritten by SD controller under Linux.

    - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't
      get automatically reserved. Solution is to add it as a reserved memory area in
      ACPI.

    - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this
      platform was made as part of: http://review.coreboot.org/#/c/3167/3

    - Once approved a follow-on patch for other southbridges using a non-standard BAR for
      the spi controller.

Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3270
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'
Siyuan Wang [Fri, 31 May 2013 11:36:30 +0000 (19:36 +0800)]
AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'

This issue can be reproduced in Linux by the following steps:
1) use pm-suspend to suspend.
2) use USB keyboard to wake up.
3) use pm-suspend to suspend. FAIL To SUSPEND.

The cause of this issue is:
USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event,
but this bit is not clear after wake up. So OS thinks there is a
wake up signal and wake up immediately.

In this patch, I add AcpiGpe0Blk using MMIO access and write 1
on bit 11. I have tested on Parmer.

Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3347
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Llano, Brazos boards: Use `sizeof(var)` to get its size
Paul Menzel [Tue, 14 May 2013 08:06:47 +0000 (10:06 +0200)]
AMD Llano, Brazos boards: Use `sizeof(var)` to get its size

Change `sizeof(type) * n`, where n is the number of array
elements, to `sizeof(variable)` to directly get the size of the
variable (struct, array). Determining the size by counting array
elements is error prone and unnecessary.

Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe
config« [1] contains the same change and is ported over. In
the commit message Rudolf makes the following comment.

»Not sure why the copy is needed instead of direct reference.
Maybe it has something to do with CAR?«

Testing on the ASRock E350M1, no regressions were noticed.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3248
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
4 years agoAMD Trinity boards: Use `sizeof(var)` to get its size
Rudolf Marek [Fri, 3 May 2013 22:08:34 +0000 (00:08 +0200)]
AMD Trinity boards: Use `sizeof(var)` to get its size

Change `sizeof(type) * n`, where n is the number of array
elements, to `sizeof(variable)` to directly get the size of the
variable (struct, array). Determining the size by counting array
elements is error prone and unnecessary.

Not sure why the copy is needed instead of direct reference.
Maybe it has something to do with CAR?

These changes are based on Rudolf’s original patch »ASUS F2A85-M:
Correct and clean up PCIe config« [1], where it was just done for
the ASUS board.

[1] http://review.coreboot.org/#/c/3194/

Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3247
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
4 years agoqemu: remove vga hook
Gerd Hoffmann [Wed, 29 May 2013 12:53:03 +0000 (14:53 +0200)]
qemu: remove vga hook

Extra care for the qemu vga should not be needed any more.
Since release 0.12 qemu loads the vgabios into the PCI ROM
bar, so everything works exactly like it does on real hardware.

Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agocpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMER
Christian Gmeiner [Mon, 27 May 2013 06:54:25 +0000 (08:54 +0200)]
cpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMER

The following is an excerpt from serial log of the Bachmann OT200.

$ grep usec coreboot_log
clocks_per_usec: 500
Root Device init 48034 usecs
CPU_CLUSTER: 0 init 133251 usecs
PCI: 00:01.0 init 33376 usecs
PCI: 00:01.1 init 9930 usecs
PCI: 00:01.2 init 9929 usecs
PCI: 00:04.0 init 9929 usecs
PCI: 00:0f.0 init 185788 usecs
PCI: 00:0f.2 init 21473 usecs
PCI: 00:0f.3 init 9930 usecs
PCI: 00:0f.4 init 9930 usecs
PCI: 00:0f.5 init 9930 usecs
PCI: 00:0f.6 init 9930 usecs
PCI: 00:0f.7 init 9929 usecs

Change-Id: I4d0805c4cf8fcb25ec107615787fc6da0c945a30
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3308
Tested-by: build bot (Jenkins)
4 years agoutil/inteltool: Add support for mobile 5 chipset
Vladimir Serbinenko [Sun, 31 Mar 2013 11:51:37 +0000 (13:51 +0200)]
util/inteltool: Add support for mobile 5 chipset

Dump registers on mobile 5. Successfully tested on X201.

Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/2993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
4 years agobeaglebone: initial Kconfig and Makefiles
Gabe Black [Sun, 26 May 2013 14:15:57 +0000 (07:15 -0700)]
beaglebone: initial Kconfig and Makefiles

Initial structure of Beaglebone port

Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoGet buildgcc to behave reasonably with the -p choice.
Ronald G. Minnich [Sun, 26 May 2013 12:33:35 +0000 (05:33 -0700)]
Get buildgcc to behave reasonably with the -p choice.

buildgcc has many wrong choices, and two right ones,
but you would never guess that. It's even more
frustrating when it spends lots of time building a
full tool chain and you find out it's not the one you
wanted and, still worse, you've forgotten what it does want
and, even worse, it won't f-ing tell you what the two
right choices are!.

Have it tell you when you've done something wrong, and have it
make reasonable decisions when you say things like
-p arm
instead of
-p armv7a-eabi

This change lowers my blood pressure 10 points.

Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3292
Tested-by: build bot (Jenkins)
4 years agoLenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console
Paul Menzel [Mon, 29 Apr 2013 21:21:07 +0000 (23:21 +0200)]
Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM console

Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console
support by copying GNUtoo’s commit for the Lenovo ThinkPad X60.

    commit 4560ca5003fe38a066616e8de1a8a414284750fd
    Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
    Date:   Fri Apr 26 12:21:41 2013 +0200

        Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support.

        Reviewed-on: http://review.coreboot.org/3142

Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3187
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Nico Huber <nico.huber@secunet.com>
4 years agosnow: Add a name to the serial console UART choice block.
Gabe Black [Sun, 26 May 2013 09:31:56 +0000 (11:31 +0200)]
snow: Add a name to the serial console UART choice block.

This allows other boards to have the same choice block without confusing
kconfig.

Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3293
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
4 years agokconfig: fix choice dependency check
Roman Zippel [Fri, 29 Feb 2008 04:10:24 +0000 (05:10 +0100)]
kconfig: fix choice dependency check

Properly check the dependency of choices as a group.
Also fix that sym_check_deps() correctly terminates the dependency loop
error check (otherwise it would continue printing the dependency chain).

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
=======

Cherry-picked from the Linux kernel.

Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3290
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agokconfig: reversed borderlines in inputbox
Roel Kluin [Thu, 20 Mar 2008 20:30:32 +0000 (21:30 +0100)]
kconfig: reversed borderlines in inputbox

Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box()
Makes the inputbox look like expected

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
=======

Cherry-picked from the Linux kernel.

Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agokconfig: add named choice group
Roman Zippel [Fri, 29 Feb 2008 04:11:50 +0000 (05:11 +0100)]
kconfig: add named choice group

As choice dependency are now fully checked, it's quite easy to add support
for named choices. This lifts the restriction that a choice value can only
appear once, although it still has to be within the same group,
but multiple choices can be joined by giving them a name.
While at it I cleaned up a little the choice type logic to simplify it a
bit.

Signed-off-by: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
=======

Cherry-picked from the Linux kernel.

Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3291
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoIntel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`
Ronald G. Minnich [Wed, 8 May 2013 15:08:55 +0000 (17:08 +0200)]
Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`

multiply_to_tsc was being copied everywhere, which is bad
practice. Put it in the tsc.h include file where it belongs.
Delete the copies of it.

Per secunet, no copyright notice is needed.

This might be a good time to get a copyright notice into tsc.h
anyway.

Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3242
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
4 years agocpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER
Paul Menzel [Wed, 1 May 2013 14:36:56 +0000 (16:36 +0200)]
cpu/amd/agesa/Kconfig: Select LAPIC_MONOTONIC_TIMER

Thanks to Aaron Durbin coreboot provides monotonic timers. Select
the LAPIC monotonic timer for the AMD AGESA CPUs.

The following is an excerpt from serial log of the ASRock E350M1.

    $ grep usec seriallog-20130502_100902.log
    01.016: Root Device init 1578 usecs
    01.029: CPU_CLUSTER: 0 init 112415 usecs
    01.029: PCI: 00:00.0 init 3240 usecs
    01.088: PCI: 00:01.0 init 104572 usecs
    01.088: PCI: 00:01.1 init 1663 usecs
    01.088: PCI: 00:11.0 init 1662 usecs
    01.088: PCI: 00:14.0 init 1662 usecs
    01.088: PCI: 00:14.3 init 8665 usecs
    01.088: PCI: 00:14.4 init 1665 usecs
    01.088: PCI: 00:18.0 init 1662 usecs
    01.088: PCI: 00:18.1 init 1663 usecs
    01.088: PCI: 00:18.2 init 1663 usecs
    01.088: PCI: 00:18.3 init 1663 usecs
    01.088: PCI: 00:18.4 init 1663 usecs
    01.088: PCI: 00:18.5 init 1665 usecs
    01.088: PCI: 00:18.6 init 1664 usecs
    01.088: PCI: 00:18.7 init 1663 usecs
    01.088: PNP: 002e.2 init 1576 usecs
    01.088: PNP: 002e.5 init 1577 usecs
    01.088: PNP: 002e.a init 1590 usecs
    01.088: PNP: 002e.b init 30144 usecs
    01.088: PCI: 03:00.0 init 1663 usecs

So the graphics device needs around 100 ms for being initialized.

The full serial log is in the Gerrit comments.

Change-Id: Ia7b3012e51fcf94b0f22290cdef2b4424295ad6d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3172
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
4 years agocpu/intel/haswell/Kconfig: Intend help text with two spaces
Paul Menzel [Mon, 13 May 2013 21:06:34 +0000 (23:06 +0200)]
cpu/intel/haswell/Kconfig: Intend help text with two spaces

Commit »haswell: 24MHz monotonic time implementation« (c46cc6f1) [1]
added the Kconfig variable `MONOTONIC_TIMER_MSR` with a help text,
but only used one space instead of the suggested two spaces for
indentation. So add one space.

»Lines under a "config" definition are indented with one tab, while
help text is indented an additional two spaces.« [2]

[1] http://review.coreboot.org/3153
[2] https://www.kernel.org/doc/Documentation/CodingStyle
    (Chapter 10: Kconfig configuration files)

Change-Id: I39cf356bfd54c66a2f1b837c6667dcc915e41f29
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3262
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
4 years agoinclude/timer.h: Fix typo in in*iti*alize in comment
Paul Menzel [Mon, 13 May 2013 21:59:20 +0000 (23:59 +0200)]
include/timer.h: Fix typo in in*iti*alize in comment

Correct a typo in a comment introduced in commit »coreboot:
introduce monotonic timer API« (a421791d) [1].

[1] http://review.coreboot.org/3152

Change-Id: Ia0abc5304547d419478db1ae37b5525406fa19cc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3261
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agoIntel Sandy Bridge: udelay.c: Change comparison from <= to <
Paul Menzel [Fri, 17 May 2013 15:25:25 +0000 (17:25 +0200)]
Intel Sandy Bridge: udelay.c: Change comparison from <= to <

Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.

The reason for this is that a wrong comparison > was used.

The following commit

    commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141
    Author: Sven Schnelle <svens@stackframe.org>
    Date:   Tue Jan 10 12:16:38 2012 +0100

        i945: fix tsc udelay()

        Reviewed-on: http://review.coreboot.org/530

fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.

    commit 00636b0daefc3c499990744226a0e1a316d71731
    Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
    Date:   Wed Apr 4 00:08:51 2012 +0200

        Add support for Intel Sandybridge CPU (northbridge part)

        Reviewed-on: http://review.coreboot.org/854

As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].

[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c

Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
4 years agoKconfig: Remove duplicate entry for `USE_OPTION_TABLE`
Paul Menzel [Wed, 1 May 2013 14:21:53 +0000 (16:21 +0200)]
Kconfig: Remove duplicate entry for `USE_OPTION_TABLE`

The following commit

    commit eb50c7d922e91f0247b3705eccb2d2eec638c277
    Author: Edwin Beasant <edwin_beasant@virtensys.com>
    Date:   Tue Jul 6 21:05:04 2010 +0000

    Re-integrate "USE_OPTION_TABLE" code.

added a duplicate entry `config USE_OPTION_TABLE`. Remove it again.

Change-Id: I3ff64c360bad531439e74fa1b25a06c4a447a33f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3165
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
4 years agointel/gm45: Add more debug output to read/write training
Nico Huber [Tue, 14 May 2013 10:28:42 +0000 (12:28 +0200)]
intel/gm45: Add more debug output to read/write training

Add debug output for the timing values of the edges found during
read and write training.

Now, output for one DIMM of DDR3-1066 in a roda/rk9 looks like:

[...]
Lower bound for byte lane 0 on channel 0: 0.0
Upper bound for byte lane 0 on channel 0: 8.4
Final timings for byte lane 0 on channel 0: 4.2
Lower bound for byte lane 1 on channel 0: 0.0
Upper bound for byte lane 1 on channel 0: 10.2
Final timings for byte lane 1 on channel 0: 5.1
Lower bound for byte lane 2 on channel 0: 0.0
Upper bound for byte lane 2 on channel 0: 7.5
Final timings for byte lane 2 on channel 0: 3.6
Lower bound for byte lane 3 on channel 0: 0.0
Upper bound for byte lane 3 on channel 0: 11.4
Final timings for byte lane 3 on channel 0: 5.6
Lower bound for byte lane 4 on channel 0: 0.0
Upper bound for byte lane 4 on channel 0: 9.4
Final timings for byte lane 4 on channel 0: 4.6
Lower bound for byte lane 5 on channel 0: 0.0
Upper bound for byte lane 5 on channel 0: 11.2
Final timings for byte lane 5 on channel 0: 5.5
Lower bound for byte lane 6 on channel 0: 0.0
Upper bound for byte lane 6 on channel 0: 8.4
Final timings for byte lane 6 on channel 0: 4.2
Lower bound for byte lane 7 on channel 0: 0.0
Upper bound for byte lane 7 on channel 0: 10.4
Final timings for byte lane 7 on channel 0: 5.2
Lower bound for group 0 on channel 0: 1.7.5
Upper bound for group 0 on channel 0: 2.2.2
Final timings for group 0 on channel 0: 1.10.7
Lower bound for group 1 on channel 0: 1.6.1
Upper bound for group 1 on channel 0: 2.0.2
Final timings for group 1 on channel 0: 1.9.1
Lower bound for group 2 on channel 0: 2.0.7
Upper bound for group 2 on channel 0: 2.8.1
Final timings for group 2 on channel 0: 2.4.4
Lower bound for group 3 on channel 0: 2.4.7
Upper bound for group 3 on channel 0: 3.0.0
Final timings for group 3 on channel 0: 2.8.3
[...]

Final timings are always the average of the two bounds. The last dots
separate eights (not decimals) and the middles are elenvenths or twelfths
depending on the clock speed (twelfths in this case).

Change-Id: Idb7c84b514716c7265b94890c39b7225de7800dc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3257
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/gm45: Handle overflows during DDR3 write training
Nico Huber [Tue, 14 May 2013 10:15:05 +0000 (12:15 +0200)]
intel/gm45: Handle overflows during DDR3 write training

We halted the machine on any overflow during the write training.
However, overflows during the search for a good to bad edge are
non-fatal, and should be ignored.

Change-Id: I45ccbabc214e208974039246d806b0d2ca2fdc03
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3256
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/gm45: Refactor DDR3 write training
Nico Huber [Tue, 14 May 2013 09:58:44 +0000 (11:58 +0200)]
intel/gm45: Refactor DDR3 write training

Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Id19be4588ad8984935040d9bcba4d7c5f2e1114f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3255
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/gm45: Handle overflows during DDR3 read training
Nico Huber [Tue, 14 May 2013 09:25:59 +0000 (11:25 +0200)]
intel/gm45: Handle overflows during DDR3 read training

We halted the machine on any overflow during the read training. However,
overflows during the search for a good to bad edge are non-fatal, and
should be ignored.

Change-Id: I77085840ade25bce955480689c84603334113d1f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3254
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/gm45: Refactor DDR3 read training
Nico Huber [Tue, 14 May 2013 09:43:03 +0000 (11:43 +0200)]
intel/gm45: Refactor DDR3 read training

Split some code in individual functions. It's the refactoring part of
a bigger change, following...

Change-Id: Ied551a011eaf22f6f8f6db0044de3634134f0b37
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3253
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/gm45: Fix interpretation of VT-d disable bit
Nico Huber [Tue, 14 May 2013 09:02:43 +0000 (11:02 +0200)]
intel/gm45: Fix interpretation of VT-d disable bit

When configuring the GTT size for the integrated graphics, the state
of VT-d was read wrong. Bit 48 of CAPID0 (D0F0) is set when VT-d is
_disabled_.

In the log of a VT-d enabled roda/rk9 we have now:

[...]
VT-d enabled
[...]
IGD decoded, subtracting 32M UMA and 4M GTT
[...]

Without this patch, only 2M GTT were reported.

Change-Id: I87582c18f4769c2a05be86936d865c0d1fb35966
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agointel/i5000: Remove unused copy of udelay.c
Nico Huber [Fri, 17 May 2013 13:58:35 +0000 (15:58 +0200)]
intel/i5000: Remove unused copy of udelay.c

It's a copy from i945 and looks like not beeing included in a
build at all.

If you should ever want to use that file for the Intel 5000,
please copy it from another chipset like the Intel 945 as it
is going to be improved.

Change-Id: I5c113bb0b2fed7b93feb3dcb1b5d962e1442963a
Reported-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build
Paul Menzel [Mon, 6 May 2013 13:18:57 +0000 (15:18 +0200)]
AMD AGESA Hudson: Include `stdint.h` and `io.h` to fix build

Apparently the files `smbus.{h,c}`, where never used and therefore
build beforehand. Needing one function in them for the ASUS F2A85-M
the build fails as some headers are missing. Including the headers
`stdint.h` and `io.h` fixes the following errors.

    […]
        CC         southbridge/amd/agesa/hudson/smbus.romstage.o
    In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0:
    src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8'
    src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32'
    src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay':
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration]
    src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration]
    […]

Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and
should be fixed. Even better, as these function do not differ
between most boards, the file should be moved out from the
specific southbridge directories.

[1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I285101fa06a365da44fa27b688c536e614d57f50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3202
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
4 years agoASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case
Paul Menzel [Sun, 5 May 2013 10:09:16 +0000 (12:09 +0200)]
ASUS F2A85-M: romstage.c: Set RAM voltage for non 1.5 Volt case

Currently the code in the if statement

    if (!byte)
     do_smbus_write_byte(0xb20, 0x15, 0x3, byte);

only gets executed if `byte == 0x0`, that means only in the
default case where RAM voltage is 1.5 Volts. But the RAM voltage
should be changed when configured for the non-default case.

So negate the predicate to alter the RAM voltage for the
non-default cases.

To prevent the build error

    OBJCOPY    cbfs/fallback/coreboot_ram.elf
    coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
    /srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1

add `southbridge/amd/agesa/hudson/smbus.c` providing the function
`do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
actually be used after the needed header files are included in a
previous commit.

Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3200
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
4 years agoMake: Use unaltered object list for dependency inclusion
Nico Huber [Wed, 15 May 2013 09:47:51 +0000 (11:47 +0200)]
Make: Use unaltered object list for dependency inclusion

It looks like the inclusion of dependency files was broken for all
ramstage objects since the list of those gets processed through the
ramstage-postprocess macro. Fix that by taking the unaltered list
for dependency files.

The output of `make printall` (look for DEPENDENCIES=) shows which
dependency files will be included.

See also:

    commit 79f9010e80a04f2e0fb0cca5759e3215dff79aff
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sun Nov 25 14:31:08 2012 +0100

        build system: Add hook to postprocess classes (object lists)

and:

    commit f33e395213f0516a9256f33ede4c6bba3babb0e9
    Author: Patrick Georgi <patrick@georgi-clan.de>
    Date:   Sun Nov 25 17:10:47 2012 +0100

        build system: Split linking into multiple steps

Change-Id: If93b1773c5d53240f98382aab11bf7f5a4649ee8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3258
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
4 years agoDrop llshell
Stefan Reinauer [Thu, 16 May 2013 19:51:07 +0000 (12:51 -0700)]
Drop llshell

This feature has not been used and was never fully integrated.
In the progress of cleaning up coreboot, let's drop it.

Change-Id: Ib40acdba30aef00a4a162f2b1009bf8b7db58bbb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3251
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
4 years agoAMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
Bruce Griffith [Thu, 16 May 2013 05:31:56 +0000 (23:31 -0600)]
AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer

The following commit

    commit 05f3b117dd44776ed17bc57318f260766039b7e8
    Author: Paul Menzel <paulepanter@users.sourceforge.net>
    Date:   Tue May 14 09:28:26 2013 +0200

        AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer

        Reviewed-on: http://review.coreboot.org/3246

changed one calculation for the size of the array PortList[] to
reflect only four elements, but neglected three additional calculations
of the size of the same table.

Correct that by setting the size for four array elements in all four
calculations.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: Ib66b7b2b388d847888663e9eb6d1c8c9d50b9939
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
4 years agoAMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer
Paul Menzel [Tue, 14 May 2013 07:28:26 +0000 (09:28 +0200)]
AMD Inagua: PlatformGnbPcie.c: Allocate exact needed size for buffer

The following commit

    commit d0790694b0a66353e5531715648ddaa1a6d577cb
    Author: Kerry Sheh <shekairui@gmail.com>
    Date:   Thu Jan 19 13:18:37 2012 +0800

        Inagua: Inagua GNB ddi lanes and pcie lanes config update

        Reviewed-on: http://review.coreboot.org/544

assigns lanes 4 and 5 to PCI device number 4, but does not
adapt the rest of the code.

After the commit above, the array `PortList []` only has four
elements, but the buffer size `AllocHeapParams.RequestedBufferSize`
is set to a size as it still has five elements.

Correct that by setting the size for four array elements.

[1] http://review.coreboot.org/#/c/3239/3/src/mainboard/amd/inagua/PlatformGnbPcie.c

Change-Id: I3ff07f308ffd417d2bf73117eda9da2a1a05f199
Reported-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3246
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
4 years agohaswell: enable cache-as-ram migration
Aaron Durbin [Fri, 10 May 2013 05:51:43 +0000 (00:51 -0500)]
haswell: enable cache-as-ram migration

The haswell code allows for vboot ramstage verification.
However, that code path relies on accessing global cache-as-ram
variables after cache-as-ram is torn down. In order to avoid
that situation enable cache-as-ram migration.

cbmemc_reinit() no longer needs to be called from romstage
because it is invoked automatically by the cache-as-ram
migration infrastructure.

Change-Id: I08998dca579c167699030e1e24ea0af8802c0758
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agocbmem console: use cache-as-ram API and cleanup
Aaron Durbin [Fri, 10 May 2013 05:45:37 +0000 (00:45 -0500)]
cbmem console: use cache-as-ram API and cleanup

Allow for automatic cache-as-ram migration for the cbmem
console. The code was refactored in the thought of making
it easier to read. The #ifdefs still exist, but they are no
longer sprinkled throughout the code. The cbmem_console_p
variable now exists globally in both romstage and ramstage.
However, the cbmem_console_p is referenced using the
cache-as-ram API. When cbmem is initialized the console
is automatically copied over by calling cbmemc_reinit()
through a callback.

Change-Id: I9f4a64e33c58b8b7318db27942e37c13804e6f2c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agochromeos: use cache-as-ram migration API for vbnv
Aaron Durbin [Fri, 10 May 2013 05:42:14 +0000 (00:42 -0500)]
chromeos: use cache-as-ram migration API for vbnv

It's possible that the vbnv global variables may be accessed
in romstage after cache-as-ram is torn down. Therefore use
the cache-as-ram migration API. Wrappers were written to
wrap the API to keep the existing code as close as possible.

Change-Id: Ia1d8932f98e00def0a44444a1ead0018a59d3d98
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
4 years agopc80/tpm: allow for cache-as-ram migration
Aaron Durbin [Fri, 10 May 2013 05:40:56 +0000 (00:40 -0500)]
pc80/tpm: allow for cache-as-ram migration

As the TPM driver can be accessed in romstage after
cache-as-ram is torn down use the cache-as-ram migration
API to dynamically determine the global variable address.

Change-Id: I149d7c130bc3677ed52282095670c07a76c34439
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>