2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #include <cpu/x86/stack.h>
29 #include <cpu/x86/mtrr.h>
30 #include <cpu/x86/cache.h>
31 #include <console/post_codes.h>
33 #define CacheSize CONFIG_DCACHE_RAM_SIZE
34 #define CacheBase CONFIG_DCACHE_RAM_BASE
36 /* Save the BIST result. */
43 orl $CR0_CacheDisable, %eax
47 /* Set the default memory type and enable fixed and variable MTRRs. */
48 movl $MTRRdefType_MSR, %ecx
50 movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
53 /* Clear all MTRRs. */
55 movl $all_mtrr_msrs, %esi
60 jz clear_fixed_var_mtrr_out
66 jmp clear_fixed_var_mtrr
70 .long MTRRfix64K_00000_MSR
71 .long MTRRfix16K_80000_MSR
72 .long MTRRfix16K_A0000_MSR
73 .long MTRRfix4K_C0000_MSR
74 .long MTRRfix4K_C8000_MSR
75 .long MTRRfix4K_D0000_MSR
76 .long MTRRfix4K_D8000_MSR
77 .long MTRRfix4K_E0000_MSR
78 .long MTRRfix4K_E8000_MSR
79 .long MTRRfix4K_F0000_MSR
80 .long MTRRfix4K_F8000_MSR
83 .long MTRRphysBase_MSR(0)
84 .long MTRRphysMask_MSR(0)
85 .long MTRRphysBase_MSR(1)
86 .long MTRRphysMask_MSR(1)
87 .long MTRRphysBase_MSR(2)
88 .long MTRRphysMask_MSR(2)
89 .long MTRRphysBase_MSR(3)
90 .long MTRRphysMask_MSR(3)
91 .long MTRRphysBase_MSR(4)
92 .long MTRRphysMask_MSR(4)
93 .long MTRRphysBase_MSR(5)
94 .long MTRRphysMask_MSR(5)
95 .long MTRRphysBase_MSR(6)
96 .long MTRRphysMask_MSR(6)
97 .long MTRRphysBase_MSR(7)
98 .long MTRRphysMask_MSR(7)
100 .long 0x000 /* NULL, end of table */
102 clear_fixed_var_mtrr_out:
103 movl $MTRRphysBase_MSR(0), %ecx
105 movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
108 movl $MTRRphysMask_MSR(0), %ecx
109 /* This assumes we never access addresses above 2^36 in CAR. */
110 movl $0x0000000f, %edx
111 movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
115 * Enable write base caching so we can do execute in place (XIP)
118 movl $MTRRphysBase_MSR(1), %ecx
121 * IMPORTANT: The following calculation _must_ be done at runtime. See
122 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
124 movl $copy_and_run, %eax
125 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
126 orl $MTRR_TYPE_WRBACK, %eax
129 movl $MTRRphysMask_MSR(1), %ecx
130 movl $0x0000000f, %edx
131 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
134 /* Set the default memory type and enable fixed and variable MTRRs. */
135 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
136 movl $MTRRdefType_MSR, %ecx
138 movl $(MTRRdefTypeEn), %eax
143 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
146 /* Read the range with lodsl. */
148 movl $CacheBase, %esi
150 movl $(CacheSize >> 2), %ecx
153 movl $CacheBase, %esi
155 movl $(CacheSize >> 2), %ecx
158 * 0x5c5c5c5c is a memory test pattern.
159 * TODO: Check if everything works with the zero pattern as well.
161 /* xorl %eax, %eax */
162 xorl $0x5c5c5c5c, %eax
167 * IMPORTANT: The following calculation _must_ be done at runtime. See
168 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
170 movl $copy_and_run, %esi
171 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
173 movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
178 * The key point of this CAR code is C7 cache does not turn into
179 * "no fill" mode, which is not compatible with general CAR code.
182 movl $(CacheBase + CacheSize - 4), %eax
205 /* Restore the BIST result. */
208 /* We need to set EBP? No need. */
210 pushl %eax /* BIST */
214 * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
215 * get STACK up, we restore that. It is only needed if we
219 /* We don't need CAR from now on. */
223 orl $CR0_CacheDisable, %eax
226 /* Set the default memory type and enable variable MTRRs. */
227 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
228 movl $MTRRdefType_MSR, %ecx
230 movl $(MTRRdefTypeEn), %eax
233 /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
234 movl $MTRRphysBase_MSR(0), %ecx
236 movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
239 movl $MTRRphysMask_MSR(0), %ecx
240 movl $0x0000000f, %edx /* AMD 40 bit 0xff */
241 movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
244 /* Cache XIP_ROM area to speedup coreboot code. */
245 movl $MTRRphysBase_MSR(1), %ecx
248 * IMPORTANT: The following calculation _must_ be done at runtime. See
249 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
251 movl $copy_and_run, %eax
252 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
253 orl $MTRR_TYPE_WRBACK, %eax
256 movl $MTRRphysMask_MSR(1), %ecx
258 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
263 andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
268 post_code(POST_PREPARE_RAMSTAGE)
269 cld /* Clear direction flag. */
271 movl $ROMSTAGE_STACK, %esp
276 post_code(POST_DEAD_CODE)