copy_and_run: drop boot_complete parameter
[gnutoo-for-coreboot:coreboot.git] / src / mainboard / amd / dinar / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18  */
19
20 #include <stdint.h>
21 #include <string.h>
22 #include <device/pci_def.h>
23 #include <device/pci_ids.h>
24 #include <arch/io.h>
25 #include <arch/stages.h>
26 #include <device/pnp_def.h>
27 #include <cpu/x86/lapic.h>
28 #include <console/console.h>
29 #include <console/loglevel.h>
30 #include "cpu/x86/bist.h"
31 #include "superio/smsc/sch4037/sch4037_early_init.c"
32 #include "superio/smsc/sio1036/sio1036_early_init.c"
33 #include "cpu/x86/lapic/boot_cpu.c"
34 #include "drivers/pc80/i8254.c"
35 #include "drivers/pc80/i8259.c"
36 #include "nb_cimx.h"
37 #include "sb_cimx.h"
38 #include "Platform.h"
39 #include <arch/cpu.h>
40
41 #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
42
43 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
44 u32 agesawrapper_amdinitmmio (void);
45 u32 agesawrapper_amdinitreset (void);
46 u32 agesawrapper_amdinitearly (void);
47 u32 agesawrapper_amdinitenv (void);
48 u32 agesawrapper_amdinitlate (void);
49 u32 agesawrapper_amdinitpost (void);
50 u32 agesawrapper_amdinitmid (void);
51
52
53
54 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
55 {
56         u32 val;
57
58         if (!cpu_init_detectedx && boot_cpu()) {
59
60                 post_code(0x30);
61
62                 sch4037_early_init (CONFIG_SIO_PORT);
63
64                 /* Detect SMSC SIO1036 LPC Debug Card status */
65                 if (detect_sio1036_chip(0x4E)) {
66                         /* Found SMSC SIO1036 LPC Debug Card */
67                         sio1036_early_init(0x4E);
68                 }
69
70                 post_code(0x31);
71                 uart_init();
72                 console_init();
73
74                 /*
75                  * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
76                  * Disable all Pcie Bridges to work around It.
77                  */
78                 sr56x0_rd890_disable_pcie_bridge();
79
80         }
81
82         post_code(0x32);
83         val = agesawrapper_amdinitmmio();
84         if (val) {
85                 printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
86         } else {
87                 printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n");
88         }
89
90         /* Halt if there was a built in self test failure */
91         post_code(0x33);
92         report_bist_failure(bist);
93
94         // Load MPB
95         val = cpuid_eax(1);
96         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
97         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
98
99         if(boot_cpu()) {
100                 post_code(0x34);
101                 sb_Poweron_Init();
102         }
103
104         post_code(0x35);
105         val = agesawrapper_amdinitreset();
106         if (val) {
107                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
108         } else {
109                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
110         }
111
112         post_code(0x36);
113         val = agesawrapper_amdinitearly ();
114         if (val) {
115                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
116         } else {
117                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
118         }
119
120         post_code(0x37);
121         nb_Poweron_Init();
122         post_code(0x38);
123         nb_Ht_Init();
124
125
126         post_code(0x39);
127         val = agesawrapper_amdinitpost ();
128         if (val) {
129                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
130         } else {
131                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
132         }
133
134         post_code(0x40);
135         val = agesawrapper_amdinitenv ();
136         if (val) {
137                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
138         } else {
139                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
140         }
141
142
143         /* Initialize i8259 pic */
144         post_code(0x41);
145         setup_i8259 ();
146
147         /* Initialize i8254 timers */
148         post_code(0x42);
149         setup_i8254 ();
150
151         post_code(0x43);
152         print_debug("Disabling cache as ram ");
153         disable_cache_as_ram();
154         print_debug("done\n");
155
156         post_code(0x44);
157         copy_and_run();
158
159         post_code(0x45);  // Should never see this post code.
160 }
161