copy_and_run: drop boot_complete parameter
[gnutoo-for-coreboot:coreboot.git] / src / mainboard / asus / f2a85-m / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
5  * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19  */
20
21 #include <stdint.h>
22 #include <string.h>
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
25 #include <arch/io.h>
26 #include <arch/stages.h>
27 #include <device/pnp_def.h>
28 #include <arch/cpu.h>
29 #include <cpu/x86/lapic.h>
30 #include <console/console.h>
31 #include <console/loglevel.h>
32 #include "agesawrapper.h"
33 #include "cpu/x86/bist.h"
34 #include "cpu/x86/lapic/boot_cpu.c"
35 #include "southbridge/amd/agesa/hudson/hudson.h"
36 #include "southbridge/amd/agesa/hudson/smbus.h"
37 #include "superio/ite/it8712f/early_serial.c"
38 #include "cpu/amd/agesa/s3_resume.h"
39 #include "src/drivers/pc80/i8254.c"
40 #include "src/drivers/pc80/i8259.c"
41 #include "cbmem.h"
42
43 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
44 void disable_cache_as_ram(void);
45
46 #define MMIO_NON_POSTED_START 0xfed00000
47 #define MMIO_NON_POSTED_END   0xfedfffff
48 #define SB_MMIO 0xFED80000
49 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
50
51 static void sbxxx_enable_48mhzout(void)
52 {
53         /* most likely programming to 48MHz out signal */
54         u32 reg32;
55         reg32 = SB_MMIO_MISC32(0x28);
56         reg32 &= 0xffc7ffff;
57         reg32 |= 0x00100000;
58         SB_MMIO_MISC32(0x28) = reg32;
59
60         reg32 = SB_MMIO_MISC32(0x40);
61         reg32 &= ~0x80u;
62         SB_MMIO_MISC32(0x40) = reg32;
63 }
64
65 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
66 {
67         u32 val;
68         u8 byte;
69         device_t dev;
70 #if CONFIG_HAVE_ACPI_RESUME
71         void *resume_backup_memory;
72 #endif
73         val = agesawrapper_amdinitmmio();
74
75         if (!cpu_init_detectedx && boot_cpu()) {
76
77                 /* enable SIO decode */
78                 dev = PCI_DEV(0, 0x14, 3);
79                 byte = pci_read_config8(dev, 0x48);
80                 byte |= 3;              /* 2e, 2f */
81                 pci_write_config8(dev, 0x48, byte);
82
83                 post_code(0x30);
84
85                 /* enable SB MMIO space */
86                 outb(0x24, 0xcd6);
87                 outb(0x1, 0xcd7);
88
89                 /* enable SIO clock */
90                 sbxxx_enable_48mhzout();
91                 it8712f_kill_watchdog();
92                 it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
93                 console_init();
94
95                 /* turn on secondary smbus at b20 */
96                 outb(0x28, 0xcd6);
97                 byte = inb(0xcd7);
98                 byte |= 1;
99                 outb(byte, 0xcd7);
100
101                 /* set DDR3 voltage */
102                 byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
103
104                 if (!byte)
105                         do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
106         }
107
108         /* Halt if there was a built in self test failure */
109         post_code(0x34);
110         report_bist_failure(bist);
111
112         /* Load MPB */
113         val = cpuid_eax(1);
114         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
115         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
116
117         post_code(0x37);
118         printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
119         val = agesawrapper_amdinitreset();
120         if(val) {
121                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
122         }
123
124         post_code(0x39);
125
126         val = agesawrapper_amdinitearly ();
127         if(val) {
128                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
129         }
130         printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
131
132 #if CONFIG_HAVE_ACPI_RESUME
133         if (!acpi_is_wakeup_early()) {          /* Check for S3 resume */
134 #endif
135                 post_code(0x40);
136                 val = agesawrapper_amdinitpost ();
137                 if(val) {
138                         printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
139                 }
140                 printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
141
142                 post_code(0x41);
143                 val = agesawrapper_amdinitenv ();
144                 if(val) {
145                         printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
146                 }
147                 printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
148                 disable_cache_as_ram();
149 #if CONFIG_HAVE_ACPI_RESUME
150         } else {                /* S3 detect */
151                 printk(BIOS_INFO, "S3 detected\n");
152
153                 post_code(0x60);
154                 printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
155                 val = agesawrapper_amdinitresume();
156                 if (val)
157                         printk(BIOS_DEBUG, "error level: %x \n", val);
158                 else
159                         printk(BIOS_DEBUG, "passed.\n");
160
161                 printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
162                 val = agesawrapper_amds3laterestore ();
163                 if (val)
164                         printk(BIOS_DEBUG, "error level: %x \n", val);
165                 else
166                         printk(BIOS_DEBUG, "passed.\n");
167
168                 post_code(0x61);
169                 printk(BIOS_DEBUG, "Find resume memory location\n");
170                 resume_backup_memory = (void *)backup_resume();
171
172                 post_code(0x62);
173                 printk(BIOS_DEBUG, "Move CAR stack.\n");
174                 move_stack_high_mem();
175                 printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
176
177                 post_code(0x63);
178                 disable_cache_as_ram();
179                 printk(BIOS_DEBUG, "CAR disabled.\n");
180                 set_resume_cache();
181
182                 /*
183                  * Copy the system memory that is in the ramstage area to the
184                  * reserved area.
185                  */
186                 if (resume_backup_memory)
187                         memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
188
189                 printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
190         }
191 #endif
192
193         /* Initialize i8259 pic */
194         post_code(0x41);
195         setup_i8259 ();
196
197         /* Initialize i8254 timers */
198         post_code(0x42);
199         setup_i8254 ();
200
201         post_code(0x50);
202         copy_and_run();
203
204         post_code(0x54);  /* Should never see this post code. */
205 }