copy_and_run: drop boot_complete parameter
[gnutoo-for-coreboot:coreboot.git] / src / mainboard / lippert / frontrunner-af / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18  */
19
20 #include <stdint.h>
21 #include <string.h>
22 #include <device/pci_def.h>
23 #include <device/pci_ids.h>
24 #include <arch/io.h>
25 #include <arch/stages.h>
26 #include <device/pnp_def.h>
27 #include <arch/cpu.h>
28 #include <cpu/x86/lapic.h>
29 #include <console/console.h>
30 #include <console/loglevel.h>
31 #include "agesawrapper.h"
32 #include "cpu/x86/bist.h"
33 #include "superio/smsc/smscsuperio/early_serial.c"
34 #include "cpu/x86/lapic/boot_cpu.c"
35 #include "drivers/pc80/i8254.c"
36 #include "drivers/pc80/i8259.c"
37 #include <cpu/x86/cache.h>
38 #include "sb_cimx.h"
39 #include "SBPLATFORM.h"
40 #include "cbmem.h"
41 #include "cpu/amd/mtrr.h"
42 #include "cpu/amd/agesa/s3_resume.h"
43
44 void disable_cache_as_ram(void); /* cache_as_ram.inc */
45 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
46
47 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
48
49 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
50 {
51         u32 val;
52
53 #if CONFIG_HAVE_ACPI_RESUME
54         void *resume_backup_memory;
55 #endif
56
57         /*
58          * All cores: allow caching of flash chip code and data
59          * (there are no cache-as-ram reliability concerns with family 14h)
60          */
61         __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
62         __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
63
64         /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
65         __writemsr (0xc0010062, 0);
66
67         if (!cpu_init_detectedx && boot_cpu()) {
68                 post_code(0x30);
69                 sb_Poweron_Init();
70
71                 post_code(0x31);
72                 smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
73                 console_init();
74         }
75
76         /* Halt if there was a built in self test failure */
77         post_code(0x34);
78         report_bist_failure(bist);
79
80         /* Load MPB */
81         val = cpuid_eax(1);
82         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
83         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
84
85         post_code(0x35);
86         printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
87         val = agesawrapper_amdinitmmio();
88         if (val)
89                 printk(BIOS_DEBUG, "error level: %x \n", val);
90         else
91                 printk(BIOS_DEBUG, "passed.\n");
92
93         post_code(0x37);
94         printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
95         val = agesawrapper_amdinitreset();
96         if (val)
97                 printk(BIOS_DEBUG, "error level: %x \n", val);
98         else
99                 printk(BIOS_DEBUG, "passed.\n");
100
101         post_code(0x39);
102         printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
103         val = agesawrapper_amdinitearly ();
104         if (val)
105                 printk(BIOS_DEBUG, "error level: %x \n", val);
106         else
107                 printk(BIOS_DEBUG, "passed.\n");
108
109 #if CONFIG_HAVE_ACPI_RESUME
110         if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
111 #endif
112                 post_code(0x40);
113                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
114                 val = agesawrapper_amdinitpost ();
115                 /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
116                  * hang, looks like DRAM re-init goes wrong, don't know why. */
117                 if (val == 7) /* fatal, amdinitenv below is going to hang */
118                         outb(0x06, 0x0cf9); /* reset system harder instead */
119                 if (val)
120                         printk(BIOS_DEBUG, "error level: %x \n", val);
121                 else
122                         printk(BIOS_DEBUG, "passed.\n");
123
124                 post_code(0x42);
125                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
126                 val = agesawrapper_amdinitenv ();
127                 if (val)
128                         printk(BIOS_DEBUG, "error level: %x \n", val);
129                 else
130                         printk(BIOS_DEBUG, "passed.\n");
131
132 #if CONFIG_HAVE_ACPI_RESUME
133         } else {                        /* S3 detect */
134                 printk(BIOS_INFO, "S3 detected\n");
135
136                 post_code(0x60);
137                 printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
138                 val = agesawrapper_amdinitresume();
139                 if (val)
140                         printk(BIOS_DEBUG, "error level: %x \n", val);
141                 else
142                         printk(BIOS_DEBUG, "passed.\n");
143
144                 printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
145                 val = agesawrapper_amds3laterestore ();
146                 if (val)
147                         printk(BIOS_DEBUG, "error level: %x \n", val);
148                 else
149                         printk(BIOS_DEBUG, "passed.\n");
150
151                 post_code(0x61);
152                 printk(BIOS_DEBUG, "Find resume memory location\n");
153                 resume_backup_memory = backup_resume();
154
155                 post_code(0x62);
156                 printk(BIOS_DEBUG, "Move CAR stack.\n");
157                 move_stack_high_mem();
158                 printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
159
160                 post_code(0x63);
161                 disable_cache_as_ram();
162                 printk(BIOS_DEBUG, "CAR disabled.\n");
163                 set_resume_cache();
164
165                 /*
166                  * Copy the system memory that is in the ramstage area to the
167                  * reserved area.
168                  */
169                 if (resume_backup_memory)
170                         memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
171
172                 printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
173         }
174 #endif
175
176         /* Initialize i8259 pic */
177         post_code(0x43);
178         setup_i8259 ();
179
180         /* Initialize i8254 timers */
181         post_code(0x44);
182         setup_i8254 ();
183
184         post_code(0x50);
185         copy_and_run();
186         printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
187
188         post_code(0x54);        /* Should never see this post code. */
189 }