copy_and_run: drop boot_complete parameter
[gnutoo-for-coreboot:coreboot.git] / src / mainboard / tyan / s8226 / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18  */
19
20 #include <lib.h>
21 #include <reset.h>
22 #include <stdint.h>
23 #include <arch/io.h>
24 #include <arch/cpu.h>
25 #include <console/console.h>
26 #include <arch/stages.h>
27 #include "cpu/x86/bist.h"
28 #include "cpu/x86/lapic/boot_cpu.c"
29 #include "agesawrapper.h"
30 #include "northbridge/amd/agesa/family10/reset_test.h"
31 #include <nb_cimx.h>
32 #include <sb_cimx.h>
33 #include "superio/nuvoton/wpcm450/wpcm450.h"
34 #include "superio/winbond/w83627dhg/w83627dhg.h"
35 #include "src/drivers/pc80/i8254.c"
36 #include "src/drivers/pc80/i8259.c"
37
38 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
39
40 #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
41 #define DUMMY_DEV PNP_DEV(0x2e, 0)
42
43 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
44 {
45         u32 val;
46
47         post_code(0x30);
48         agesawrapper_amdinitmmio();
49         post_code(0x31);
50
51         /* Halt if there was a built in self test failure */
52         post_code(0x33);
53         report_bist_failure(bist);
54
55         sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
56         w83627dhg_set_clksel_48(DUMMY_DEV);
57         w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
58         sb7xx_51xx_disable_wideio(0);
59         post_code(0x34);
60
61         uart_init();
62         post_code(0x35);
63         console_init();
64
65         val = cpuid_eax(1);
66         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
67         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
68
69         post_code(0x37);
70         val = agesawrapper_amdinitreset();
71         if (val) {
72                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
73         } else {
74                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
75         }
76
77         if (!cpu_init_detectedx && boot_cpu()) {
78                 post_code(0x38);
79                 /*
80                  * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
81                  * Disable all Pcie Bridges to work around It.
82                  */
83                 sr56x0_rd890_disable_pcie_bridge();
84                 post_code(0x39);
85                 nb_Poweron_Init();
86                 post_code(0x3A);
87                 sb_Poweron_Init();
88         }
89         post_code(0x3B);
90         val = agesawrapper_amdinitearly();
91         if(val) {
92                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
93         } else {
94                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
95         }
96
97         post_code(0x3C);
98         /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
99          * In order to access W83795G/ADG HWM using I2C protocol,
100          * we select function to SDA, SCL function (or GP33, GP32 function).
101          */
102         w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
103
104         nb_Ht_Init();
105         post_code(0x3D);
106         /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
107         if (!warm_reset_detect(0)) {
108                 print_info("...WARM RESET...\n\n\n");
109                 distinguish_cpu_resets(0);
110                 soft_reset();
111                 die("After soft_reset_x - shouldn't see this message!!!\n");
112         }
113
114         post_code(0x40);
115         val = agesawrapper_amdinitpost();
116         if (val) {
117                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
118         } else {
119                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
120         }
121
122         post_code(0x41);
123         val = agesawrapper_amdinitenv();
124         if(val) {
125                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
126         }
127         printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
128
129         post_code(0x42);
130
131         post_code(0x50);
132         print_debug("Disabling cache as ram ");
133         disable_cache_as_ram();
134         print_debug("done\n");
135
136         post_code(0x51);
137         setup_i8259 ();
138         setup_i8254 ();
139         copy_and_run();
140
141         /* We will not return,  Should never see this message and post code. */
142         print_debug("should not be here -\n");
143         post_code(0x54);
144 }
145