omap4iss: csi2: use VP16 for YUV422 8-bit
[omap4-v4l2-camera:alfredds-omap4-v4l2-camera.git] / drivers / media / video / omap4iss / iss_csi2.c
1 /*
2  * TI OMAP4 ISS V4L2 Driver - CSI PHY module
3  *
4  * Copyright (C) 2012 Texas Instruments, Inc.
5  *
6  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/delay.h>
15 #include <media/v4l2-common.h>
16 #include <linux/v4l2-mediabus.h>
17 #include <linux/mm.h>
18
19 #include "iss.h"
20 #include "iss_regs.h"
21 #include "iss_csi2.h"
22
23 /*
24  * csi2_if_enable - Enable CSI2 Receiver interface.
25  * @enable: enable flag
26  *
27  */
28 static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable)
29 {
30         struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
31
32         writel((readl(csi2->regs1 + CSI2_CTRL) & ~CSI2_CTRL_IF_EN) |
33                 (enable ? CSI2_CTRL_IF_EN : 0),
34                 csi2->regs1 + CSI2_CTRL);
35
36         currctrl->if_enable = enable;
37 }
38
39 /*
40  * csi2_recv_config - CSI2 receiver module configuration.
41  * @currctrl: iss_csi2_ctrl_cfg structure
42  *
43  */
44 static void csi2_recv_config(struct iss_csi2_device *csi2,
45                              struct iss_csi2_ctrl_cfg *currctrl)
46 {
47         u32 reg = 0;
48
49         if (currctrl->frame_mode)
50                 reg |= CSI2_CTRL_FRAME;
51         else
52                 reg &= ~CSI2_CTRL_FRAME;
53
54         if (currctrl->vp_clk_enable)
55                 reg |= CSI2_CTRL_VP_CLK_EN;
56         else
57                 reg &= ~CSI2_CTRL_VP_CLK_EN;
58
59         if (currctrl->vp_only_enable)
60                 reg |= CSI2_CTRL_VP_ONLY_EN;
61         else
62                 reg &= ~CSI2_CTRL_VP_ONLY_EN;
63
64         reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK;
65         reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT;
66
67         if (currctrl->ecc_enable)
68                 reg |= CSI2_CTRL_ECC_EN;
69         else
70                 reg &= ~CSI2_CTRL_ECC_EN;
71
72         /*
73          * Set MFlag assertion boundaries to:
74          * Low: 4/8 of FIFO size
75          * High: 6/8 of FIFO size
76          */
77         reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK);
78         reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) |
79                (4 << CSI2_CTRL_MFLAG_LEVL_SHIFT);
80
81         /* Generation of 16x64-bit bursts (Recommended) */
82         reg |= CSI2_CTRL_BURST_SIZE_EXPAND;
83
84         /* Do Non-Posted writes (Recommended) */
85         reg |= CSI2_CTRL_NON_POSTED_WRITE;
86
87         /*
88          * Enforce Little endian for all formats, including:
89          * YUV4:2:2 8-bit and YUV4:2:0 Legacy
90          */
91         reg |= CSI2_CTRL_ENDIANNESS;
92
93         writel(reg, csi2->regs1 + CSI2_CTRL);
94 }
95
96 static const unsigned int csi2_input_fmts[] = {
97         V4L2_MBUS_FMT_SGRBG10_1X10,
98         V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
99         V4L2_MBUS_FMT_SRGGB10_1X10,
100         V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8,
101         V4L2_MBUS_FMT_SBGGR10_1X10,
102         V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8,
103         V4L2_MBUS_FMT_SGBRG10_1X10,
104         V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8,
105         V4L2_MBUS_FMT_SBGGR8_1X8,
106         V4L2_MBUS_FMT_SGBRG8_1X8,
107         V4L2_MBUS_FMT_SGRBG8_1X8,
108         V4L2_MBUS_FMT_SRGGB8_1X8,
109         V4L2_MBUS_FMT_UYVY8_1X16,
110         V4L2_MBUS_FMT_YUYV8_1X16,
111 };
112
113 /* To set the format on the CSI2 requires a mapping function that takes
114  * the following inputs:
115  * - 3 different formats (at this time)
116  * - 2 destinations (mem, vp+mem) (vp only handled separately)
117  * - 2 decompression options (on, off)
118  * Output should be CSI2 frame format code
119  * Array indices as follows: [format][dest][decompr]
120  * Not all combinations are valid. 0 means invalid.
121  */
122 static const u16 __csi2_fmt_map[][2][2] = {
123         /* RAW10 formats */
124         {
125                 /* Output to memory */
126                 {
127                         /* No DPCM decompression */
128                         CSI2_PIX_FMT_RAW10_EXP16,
129                         /* DPCM decompression */
130                         0,
131                 },
132                 /* Output to both */
133                 {
134                         /* No DPCM decompression */
135                         CSI2_PIX_FMT_RAW10_EXP16_VP,
136                         /* DPCM decompression */
137                         0,
138                 },
139         },
140         /* RAW10 DPCM8 formats */
141         {
142                 /* Output to memory */
143                 {
144                         /* No DPCM decompression */
145                         CSI2_USERDEF_8BIT_DATA1,
146                         /* DPCM decompression */
147                         CSI2_USERDEF_8BIT_DATA1_DPCM10,
148                 },
149                 /* Output to both */
150                 {
151                         /* No DPCM decompression */
152                         CSI2_PIX_FMT_RAW8_VP,
153                         /* DPCM decompression */
154                         CSI2_USERDEF_8BIT_DATA1_DPCM10_VP,
155                 },
156         },
157         /* RAW8 formats */
158         {
159                 /* Output to memory */
160                 {
161                         /* No DPCM decompression */
162                         CSI2_PIX_FMT_RAW8,
163                         /* DPCM decompression */
164                         0,
165                 },
166                 /* Output to both */
167                 {
168                         /* No DPCM decompression */
169                         CSI2_PIX_FMT_RAW8_VP,
170                         /* DPCM decompression */
171                         0,
172                 },
173         },
174         /* YUV422 formats */
175         {
176                 /* Output to memory */
177                 {
178                         /* No DPCM decompression */
179                         CSI2_PIX_FMT_YUV422_8BIT,
180                         /* DPCM decompression */
181                         0,
182                 },
183                 /* Output to both */
184                 {
185                         /* No DPCM decompression */
186                         CSI2_PIX_FMT_YUV422_8BIT_VP16,
187                         /* DPCM decompression */
188                         0,
189                 },
190         },
191 };
192
193 /*
194  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
195  * @csi2: ISS CSI2 device
196  *
197  * Returns CSI2 physical format id
198  */
199 static u16 csi2_ctx_map_format(struct iss_csi2_device *csi2)
200 {
201         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
202         int fmtidx, destidx;
203
204         switch (fmt->code) {
205         case V4L2_MBUS_FMT_SGRBG10_1X10:
206         case V4L2_MBUS_FMT_SRGGB10_1X10:
207         case V4L2_MBUS_FMT_SBGGR10_1X10:
208         case V4L2_MBUS_FMT_SGBRG10_1X10:
209                 fmtidx = 0;
210                 break;
211         case V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8:
212         case V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8:
213         case V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8:
214         case V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8:
215                 fmtidx = 1;
216                 break;
217         case V4L2_MBUS_FMT_SBGGR8_1X8:
218         case V4L2_MBUS_FMT_SGBRG8_1X8:
219         case V4L2_MBUS_FMT_SGRBG8_1X8:
220         case V4L2_MBUS_FMT_SRGGB8_1X8:
221                 fmtidx = 2;
222                 break;
223         case V4L2_MBUS_FMT_UYVY8_1X16:
224         case V4L2_MBUS_FMT_YUYV8_1X16:
225                 fmtidx = 3;
226                 break;
227         default:
228                 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
229                      fmt->code);
230                 return 0;
231         }
232
233         if (!(csi2->output & CSI2_OUTPUT_IPIPEIF) &&
234             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
235                 /* Neither output enabled is a valid combination */
236                 return CSI2_PIX_FMT_OTHERS;
237         }
238
239         /* If we need to skip frames at the beginning of the stream disable the
240          * video port to avoid sending the skipped frames to the IPIPEIF.
241          */
242         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
243
244         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress];
245 }
246
247 /*
248  * csi2_set_outaddr - Set memory address to save output image
249  * @csi2: Pointer to ISS CSI2a device.
250  * @addr: 32-bit memory address aligned on 32 byte boundary.
251  *
252  * Sets the memory address where the output will be saved.
253  *
254  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
255  * boundary.
256  */
257 static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
258 {
259         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0];
260
261         ctx->ping_addr = addr;
262         ctx->pong_addr = addr;
263         writel(ctx->ping_addr,
264                csi2->regs1 + CSI2_CTX_PING_ADDR(ctx->ctxnum));
265         writel(ctx->pong_addr,
266                csi2->regs1 + CSI2_CTX_PONG_ADDR(ctx->ctxnum));
267 }
268
269 /*
270  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
271  *                      be enabled by CSI2.
272  * @format_id: mapped format id
273  *
274  */
275 static inline int is_usr_def_mapping(u32 format_id)
276 {
277         return ((format_id & 0xF0) == 0x40) ? 1 : 0;
278 }
279
280 /*
281  * csi2_ctx_enable - Enable specified CSI2 context
282  * @ctxnum: Context number, valid between 0 and 7 values.
283  * @enable: enable
284  *
285  */
286 static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable)
287 {
288         struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
289         u32 reg;
290
291         reg = readl(csi2->regs1 + CSI2_CTX_CTRL1(ctxnum));
292
293         if (enable) {
294                 unsigned int skip = 0;
295
296                 if (csi2->frame_skip)
297                         skip = csi2->frame_skip;
298                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
299                         skip = 1;
300
301                 reg &= ~CSI2_CTX_CTRL1_COUNT_MASK;
302                 reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK
303                     |  (skip << CSI2_CTX_CTRL1_COUNT_SHIFT)
304                     |  CSI2_CTX_CTRL1_CTX_EN;
305         } else {
306                 reg &= ~CSI2_CTX_CTRL1_CTX_EN;
307         }
308
309         writel(reg, csi2->regs1 + CSI2_CTX_CTRL1(ctxnum));
310         ctx->enabled = enable;
311 }
312
313 /*
314  * csi2_ctx_config - CSI2 context configuration.
315  * @ctx: context configuration
316  *
317  */
318 static void csi2_ctx_config(struct iss_csi2_device *csi2,
319                             struct iss_csi2_ctx_cfg *ctx)
320 {
321         u32 reg;
322
323         /* Set up CSI2_CTx_CTRL1 */
324         if (ctx->eof_enabled)
325                 reg = CSI2_CTX_CTRL1_EOF_EN;
326
327         if (ctx->eol_enabled)
328                 reg |= CSI2_CTX_CTRL1_EOL_EN;
329
330         if (ctx->checksum_enabled)
331                 reg |= CSI2_CTX_CTRL1_CS_EN;
332
333         writel(reg, csi2->regs1 + CSI2_CTX_CTRL1(ctx->ctxnum));
334
335         /* Set up CSI2_CTx_CTRL2 */
336         reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
337         reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT;
338
339         if (ctx->dpcm_decompress && ctx->dpcm_predictor)
340                 reg |= CSI2_CTX_CTRL2_DPCM_PRED;
341
342         if (is_usr_def_mapping(ctx->format_id))
343                 reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
344
345         writel(reg, csi2->regs1 + CSI2_CTX_CTRL2(ctx->ctxnum));
346
347         /* Set up CSI2_CTx_CTRL3 */
348         writel(ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT,
349                 csi2->regs1 + CSI2_CTX_CTRL3(ctx->ctxnum));
350
351         /* Set up CSI2_CTx_DAT_OFST */
352         reg = readl(csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum));
353         reg &= ~CSI2_CTX_DAT_OFST_MASK;
354         reg |= ctx->data_offset;
355         writel(reg, csi2->regs1 + CSI2_CTX_DAT_OFST(ctx->ctxnum));
356
357         writel(ctx->ping_addr,
358                        csi2->regs1 + CSI2_CTX_PING_ADDR(ctx->ctxnum));
359
360         writel(ctx->pong_addr,
361                        csi2->regs1 + CSI2_CTX_PONG_ADDR(ctx->ctxnum));
362 }
363
364 /*
365  * csi2_timing_config - CSI2 timing configuration.
366  * @timing: csi2_timing_cfg structure
367  */
368 static void csi2_timing_config(struct iss_csi2_device *csi2,
369                                struct iss_csi2_timing_cfg *timing)
370 {
371         u32 reg;
372
373         reg = readl(csi2->regs1 + CSI2_TIMING);
374
375         if (timing->force_rx_mode)
376                 reg |= CSI2_TIMING_FORCE_RX_MODE_IO1;
377         else
378                 reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1;
379
380         if (timing->stop_state_16x)
381                 reg |= CSI2_TIMING_STOP_STATE_X16_IO1;
382         else
383                 reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1;
384
385         if (timing->stop_state_4x)
386                 reg |= CSI2_TIMING_STOP_STATE_X4_IO1;
387         else
388                 reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1;
389
390         reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK;
391         reg |= timing->stop_state_counter <<
392                CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT;
393
394         writel(reg, csi2->regs1 + CSI2_TIMING);
395 }
396
397 /*
398  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
399  * @enable: Enable/disable CSI2 Context interrupts
400  */
401 static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable)
402 {
403         u32 reg = CSI2_CTX_IRQ_FE;
404         int i;
405
406         if (csi2->use_fs_irq)
407                 reg |= CSI2_CTX_IRQ_FS;
408
409         for (i = 0; i < 8; i++) {
410                 writel(reg, csi2->regs1 + CSI2_CTX_IRQSTATUS(i));
411                 if (enable)
412                         writel(readl(csi2->regs1 + CSI2_CTX_IRQENABLE(i)) | reg,
413                                 csi2->regs1 + CSI2_CTX_IRQENABLE(i));
414                 else
415                         writel(readl(csi2->regs1 + CSI2_CTX_IRQENABLE(i)) &
416                                 ~reg,
417                                 csi2->regs1 + CSI2_CTX_IRQENABLE(i));
418         }
419 }
420
421 /*
422  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
423  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
424  */
425 static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable)
426 {
427         u32 reg;
428         reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT |
429                 CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER |
430                 CSI2_COMPLEXIO_IRQ_STATEULPM5 |
431                 CSI2_COMPLEXIO_IRQ_ERRCONTROL5 |
432                 CSI2_COMPLEXIO_IRQ_ERRESC5 |
433                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 |
434                 CSI2_COMPLEXIO_IRQ_ERRSOTHS5 |
435                 CSI2_COMPLEXIO_IRQ_STATEULPM4 |
436                 CSI2_COMPLEXIO_IRQ_ERRCONTROL4 |
437                 CSI2_COMPLEXIO_IRQ_ERRESC4 |
438                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 |
439                 CSI2_COMPLEXIO_IRQ_ERRSOTHS4 |
440                 CSI2_COMPLEXIO_IRQ_STATEULPM3 |
441                 CSI2_COMPLEXIO_IRQ_ERRCONTROL3 |
442                 CSI2_COMPLEXIO_IRQ_ERRESC3 |
443                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 |
444                 CSI2_COMPLEXIO_IRQ_ERRSOTHS3 |
445                 CSI2_COMPLEXIO_IRQ_STATEULPM2 |
446                 CSI2_COMPLEXIO_IRQ_ERRCONTROL2 |
447                 CSI2_COMPLEXIO_IRQ_ERRESC2 |
448                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 |
449                 CSI2_COMPLEXIO_IRQ_ERRSOTHS2 |
450                 CSI2_COMPLEXIO_IRQ_STATEULPM1 |
451                 CSI2_COMPLEXIO_IRQ_ERRCONTROL1 |
452                 CSI2_COMPLEXIO_IRQ_ERRESC1 |
453                 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 |
454                 CSI2_COMPLEXIO_IRQ_ERRSOTHS1;
455         writel(reg, csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS);
456         if (enable)
457                 reg |= readl(csi2->regs1 + CSI2_COMPLEXIO_IRQENABLE);
458         else
459                 reg = 0;
460         writel(reg, csi2->regs1 + CSI2_COMPLEXIO_IRQENABLE);
461 }
462
463 /*
464  * csi2_irq_status_set - Enables CSI2 Status IRQs.
465  * @enable: Enable/disable CSI2 Status interrupts
466  */
467 static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable)
468 {
469         u32 reg;
470         reg = CSI2_IRQ_OCP_ERR |
471                 CSI2_IRQ_SHORT_PACKET |
472                 CSI2_IRQ_ECC_CORRECTION |
473                 CSI2_IRQ_ECC_NO_CORRECTION |
474                 CSI2_IRQ_COMPLEXIO_ERR |
475                 CSI2_IRQ_FIFO_OVF |
476                 CSI2_IRQ_CONTEXT0;
477         writel(reg, csi2->regs1 + CSI2_IRQSTATUS);
478         if (enable)
479                 reg |= readl(csi2->regs1 + CSI2_IRQENABLE);
480         else
481                 reg = 0;
482
483         writel(reg, csi2->regs1 + CSI2_IRQENABLE);
484 }
485
486 /*
487  * omap4iss_csi2_reset - Resets the CSI2 module.
488  *
489  * Must be called with the phy lock held.
490  *
491  * Returns 0 if successful, or -EBUSY if power command didn't respond.
492  */
493 int omap4iss_csi2_reset(struct iss_csi2_device *csi2)
494 {
495         u8 soft_reset_retries = 0;
496         u32 reg;
497         int i;
498
499         if (!csi2->available)
500                 return -ENODEV;
501
502         if (csi2->phy->phy_in_use)
503                 return -EBUSY;
504
505         writel(readl(csi2->regs1 + CSI2_SYSCONFIG) |
506                 CSI2_SYSCONFIG_SOFT_RESET,
507                 csi2->regs1 + CSI2_SYSCONFIG);
508
509         do {
510                 reg = readl(csi2->regs1 + CSI2_SYSSTATUS) &
511                                     CSI2_SYSSTATUS_RESET_DONE;
512                 if (reg == CSI2_SYSSTATUS_RESET_DONE)
513                         break;
514                 soft_reset_retries++;
515                 if (soft_reset_retries < 5)
516                         usleep_range(100, 100);
517         } while (soft_reset_retries < 5);
518
519         if (soft_reset_retries == 5) {
520                 printk(KERN_ERR "CSI2: Soft reset try count exceeded!\n");
521                 return -EBUSY;
522         }
523
524         writel(readl(csi2->regs1 + CSI2_COMPLEXIO_CFG) |
525                 CSI2_COMPLEXIO_CFG_RESET_CTRL,
526                 csi2->regs1 + CSI2_COMPLEXIO_CFG);
527
528         i = 100;
529         do {
530                 reg = readl(csi2->phy->phy_regs + REGISTER1)
531                     & REGISTER1_RESET_DONE_CTRLCLK;
532                 if (reg == REGISTER1_RESET_DONE_CTRLCLK)
533                         break;
534                 usleep_range(100, 100);
535         } while (--i > 0);
536
537         if (i == 0) {
538                 printk(KERN_ERR
539                        "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
540                 return -EBUSY;
541         }
542
543         writel((readl(csi2->regs1 + CSI2_SYSCONFIG) &
544                 ~(CSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
545                   CSI2_SYSCONFIG_AUTO_IDLE)) |
546                 CSI2_SYSCONFIG_MSTANDBY_MODE_NO,
547                 csi2->regs1 + CSI2_SYSCONFIG);
548
549         return 0;
550 }
551
552 static int csi2_configure(struct iss_csi2_device *csi2)
553 {
554         const struct iss_v4l2_subdevs_group *pdata;
555         struct iss_csi2_timing_cfg *timing = &csi2->timing[0];
556         struct v4l2_subdev *sensor;
557         struct media_pad *pad;
558
559         /*
560          * CSI2 fields that can be updated while the context has
561          * been enabled or the interface has been enabled are not
562          * updated dynamically currently. So we do not allow to
563          * reconfigure if either has been enabled
564          */
565         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
566                 return -EBUSY;
567
568         pad = media_entity_remote_source(&csi2->pads[CSI2_PAD_SINK]);
569         sensor = media_entity_to_v4l2_subdev(pad->entity);
570         pdata = sensor->host_priv;
571
572         csi2->frame_skip = 0;
573         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
574
575         csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
576         csi2->ctrl.frame_mode = ISS_CSI2_FRAME_IMMEDIATE;
577         csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
578
579         timing->force_rx_mode = 1;
580         timing->stop_state_16x = 1;
581         timing->stop_state_4x = 1;
582         timing->stop_state_counter = 0x1FF;
583
584         /*
585          * The CSI2 receiver can't do any format conversion except DPCM
586          * decompression, so every set_format call configures both pads
587          * and enables DPCM decompression as a special case:
588          */
589         if (csi2->formats[CSI2_PAD_SINK].code !=
590             csi2->formats[CSI2_PAD_SOURCE].code)
591                 csi2->dpcm_decompress = true;
592         else
593                 csi2->dpcm_decompress = false;
594
595         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
596
597         if (csi2->video_out.bpl_padding == 0)
598                 csi2->contexts[0].data_offset = 0;
599         else
600                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
601
602         /*
603          * Enable end of frame and end of line signals generation for
604          * context 0. These signals are generated from CSI2 receiver to
605          * qualify the last pixel of a frame and the last pixel of a line.
606          * Without enabling the signals CSI2 receiver writes data to memory
607          * beyond buffer size and/or data line offset is not handled correctly.
608          */
609         csi2->contexts[0].eof_enabled = 1;
610         csi2->contexts[0].eol_enabled = 1;
611
612         csi2_irq_complexio1_set(csi2, 1);
613         csi2_irq_ctx_set(csi2, 1);
614         csi2_irq_status_set(csi2, 1);
615
616         /* Set configuration (timings, format and links) */
617         csi2_timing_config(csi2, timing);
618         csi2_recv_config(csi2, &csi2->ctrl);
619         csi2_ctx_config(csi2, &csi2->contexts[0]);
620
621         return 0;
622 }
623
624 /*
625  * csi2_print_status - Prints CSI2 debug information.
626  */
627 #define CSI2_PRINT_REGISTER(iss, regs, name)\
628         dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \
629                 readl(regs + CSI2_##name))
630
631 static void csi2_print_status(struct iss_csi2_device *csi2)
632 {
633         struct iss_device *iss = csi2->iss;
634
635         if (!csi2->available)
636                 return;
637
638         dev_dbg(iss->dev, "-------------CSI2 Register dump-------------\n");
639
640         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSCONFIG);
641         CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSSTATUS);
642         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQENABLE);
643         CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQSTATUS);
644         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTRL);
645         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_H);
646         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_CFG);
647         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQSTATUS);
648         CSI2_PRINT_REGISTER(iss, csi2->regs1, SHORT_PACKET);
649         CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQENABLE);
650         CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_P);
651         CSI2_PRINT_REGISTER(iss, csi2->regs1, TIMING);
652         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL1(0));
653         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL2(0));
654         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_DAT_OFST(0));
655         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PING_ADDR(0));
656         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PONG_ADDR(0));
657         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQENABLE(0));
658         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQSTATUS(0));
659         CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL3(0));
660
661         dev_dbg(iss->dev, "--------------------------------------------\n");
662 }
663
664 /* -----------------------------------------------------------------------------
665  * Interrupt handling
666  */
667
668 /*
669  * csi2_isr_buffer - Does buffer handling at end-of-frame
670  * when writing to memory.
671  */
672 static void csi2_isr_buffer(struct iss_csi2_device *csi2)
673 {
674         struct iss_buffer *buffer;
675
676         csi2_ctx_enable(csi2, 0, 0);
677
678         buffer = omap4iss_video_buffer_next(&csi2->video_out);
679
680         /*
681          * Let video queue operation restart engine if there is an underrun
682          * condition.
683          */
684         if (buffer == NULL)
685                 return;
686
687         csi2_set_outaddr(csi2, buffer->iss_addr);
688         csi2_ctx_enable(csi2, 0, 1);
689 }
690
691 static void csi2_isr_ctx(struct iss_csi2_device *csi2,
692                          struct iss_csi2_ctx_cfg *ctx)
693 {
694         unsigned int n = ctx->ctxnum;
695         u32 status;
696
697         status = readl(csi2->regs1 + CSI2_CTX_IRQSTATUS(n));
698         writel(status, csi2->regs1 + CSI2_CTX_IRQSTATUS(n));
699
700         /* Propagate frame number */
701         if (status & CSI2_CTX_IRQ_FS) {
702                 struct iss_pipeline *pipe =
703                                      to_iss_pipeline(&csi2->subdev.entity);
704                 if (pipe->do_propagation)
705                         atomic_inc(&pipe->frame_number);
706         }
707
708         if (!(status & CSI2_CTX_IRQ_FE))
709                 return;
710
711         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
712          * automatically disabled, as the frame skip count has been programmed
713          * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
714          *
715          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
716          * but it turned out that the interrupt is only generated when the CSI2
717          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
718          * correctly and reaches 0 when data is forwarded to the video port only
719          * but no interrupt arrives). Maybe a CSI2 hardware bug.
720          */
721         if (csi2->frame_skip) {
722                 csi2->frame_skip--;
723                 if (csi2->frame_skip == 0) {
724                         ctx->format_id = csi2_ctx_map_format(csi2);
725                         csi2_ctx_config(csi2, ctx);
726                         csi2_ctx_enable(csi2, n, 1);
727                 }
728                 return;
729         }
730
731         if (csi2->output & CSI2_OUTPUT_MEMORY)
732                 csi2_isr_buffer(csi2);
733 }
734
735 /*
736  * omap4iss_csi2_isr - CSI2 interrupt handling.
737  */
738 void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
739 {
740         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
741         u32 csi2_irqstatus, cpxio1_irqstatus;
742         struct iss_device *iss = csi2->iss;
743
744         if (!csi2->available)
745                 return;
746
747         csi2_irqstatus = readl(csi2->regs1 + CSI2_IRQSTATUS);
748         writel(csi2_irqstatus, csi2->regs1 + CSI2_IRQSTATUS);
749
750         /* Failure Cases */
751         if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) {
752                 cpxio1_irqstatus = readl(csi2->regs1 +
753                                          CSI2_COMPLEXIO_IRQSTATUS);
754                 writel(cpxio1_irqstatus,
755                         csi2->regs1 + CSI2_COMPLEXIO_IRQSTATUS);
756                 dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ "
757                         "%x\n", cpxio1_irqstatus);
758                 pipe->error = true;
759         }
760
761         if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR |
762                               CSI2_IRQ_SHORT_PACKET |
763                               CSI2_IRQ_ECC_NO_CORRECTION |
764                               CSI2_IRQ_COMPLEXIO_ERR |
765                               CSI2_IRQ_FIFO_OVF)) {
766                 dev_dbg(iss->dev, "CSI2 Err:"
767                         " OCP:%d,"
768                         " Short_pack:%d,"
769                         " ECC:%d,"
770                         " CPXIO:%d,"
771                         " FIFO_OVF:%d,"
772                         "\n",
773                         (csi2_irqstatus &
774                          CSI2_IRQ_OCP_ERR) ? 1 : 0,
775                         (csi2_irqstatus &
776                          CSI2_IRQ_SHORT_PACKET) ? 1 : 0,
777                         (csi2_irqstatus &
778                          CSI2_IRQ_ECC_NO_CORRECTION) ? 1 : 0,
779                         (csi2_irqstatus &
780                          CSI2_IRQ_COMPLEXIO_ERR) ? 1 : 0,
781                         (csi2_irqstatus &
782                          CSI2_IRQ_FIFO_OVF) ? 1 : 0);
783                 pipe->error = true;
784         }
785
786         if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
787                 return;
788
789         /* Successful cases */
790         if (csi2_irqstatus & CSI2_IRQ_CONTEXT0)
791                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
792
793         if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION)
794                 dev_dbg(iss->dev, "CSI2: ECC correction done\n");
795 }
796
797 /* -----------------------------------------------------------------------------
798  * ISS video operations
799  */
800
801 /*
802  * csi2_queue - Queues the first buffer when using memory output
803  * @video: The video node
804  * @buffer: buffer to queue
805  */
806 static int csi2_queue(struct iss_video *video, struct iss_buffer *buffer)
807 {
808         struct iss_csi2_device *csi2 = container_of(video,
809                                 struct iss_csi2_device, video_out);
810
811         csi2_set_outaddr(csi2, buffer->iss_addr);
812
813         /*
814          * If streaming was enabled before there was a buffer queued
815          * or underrun happened in the ISR, the hardware was not enabled
816          * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set.
817          * Enable it now.
818          */
819         if (csi2->video_out.dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
820                 /* Enable / disable context 0 and IRQs */
821                 csi2_if_enable(csi2, 1);
822                 csi2_ctx_enable(csi2, 0, 1);
823                 iss_video_dmaqueue_flags_clr(&csi2->video_out);
824         }
825
826         return 0;
827 }
828
829 static const struct iss_video_operations csi2_issvideo_ops = {
830         .queue = csi2_queue,
831 };
832
833 /* -----------------------------------------------------------------------------
834  * V4L2 subdev operations
835  */
836
837 static struct v4l2_mbus_framefmt *
838 __csi2_get_format(struct iss_csi2_device *csi2, struct v4l2_subdev_fh *fh,
839                   unsigned int pad, enum v4l2_subdev_format_whence which)
840 {
841         if (which == V4L2_SUBDEV_FORMAT_TRY)
842                 return v4l2_subdev_get_try_format(fh, pad);
843         else
844                 return &csi2->formats[pad];
845 }
846
847 static void
848 csi2_try_format(struct iss_csi2_device *csi2, struct v4l2_subdev_fh *fh,
849                 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
850                 enum v4l2_subdev_format_whence which)
851 {
852         enum v4l2_mbus_pixelcode pixelcode;
853         struct v4l2_mbus_framefmt *format;
854         const struct iss_format_info *info;
855         unsigned int i;
856
857         switch (pad) {
858         case CSI2_PAD_SINK:
859                 /* Clamp the width and height to valid range (1-8191). */
860                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
861                         if (fmt->code == csi2_input_fmts[i])
862                                 break;
863                 }
864
865                 /* If not found, use SGRBG10 as default */
866                 if (i >= ARRAY_SIZE(csi2_input_fmts))
867                         fmt->code = V4L2_MBUS_FMT_SGRBG10_1X10;
868
869                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
870                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
871                 break;
872
873         case CSI2_PAD_SOURCE:
874                 /* Source format same as sink format, except for DPCM
875                  * compression.
876                  */
877                 pixelcode = fmt->code;
878                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK, which);
879                 memcpy(fmt, format, sizeof(*fmt));
880
881                 /*
882                  * Only Allow DPCM decompression, and check that the
883                  * pattern is preserved
884                  */
885                 info = omap4iss_video_format_info(fmt->code);
886                 if (info->uncompressed == pixelcode)
887                         fmt->code = pixelcode;
888                 break;
889         }
890
891         /* RGB, non-interlaced */
892         fmt->colorspace = V4L2_COLORSPACE_SRGB;
893         fmt->field = V4L2_FIELD_NONE;
894 }
895
896 /*
897  * csi2_enum_mbus_code - Handle pixel format enumeration
898  * @sd     : pointer to v4l2 subdev structure
899  * @fh     : V4L2 subdev file handle
900  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
901  * return -EINVAL or zero on success
902  */
903 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
904                                struct v4l2_subdev_fh *fh,
905                                struct v4l2_subdev_mbus_code_enum *code)
906 {
907         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
908         struct v4l2_mbus_framefmt *format;
909         const struct iss_format_info *info;
910
911         if (code->pad == CSI2_PAD_SINK) {
912                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
913                         return -EINVAL;
914
915                 code->code = csi2_input_fmts[code->index];
916         } else {
917                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SINK,
918                                            V4L2_SUBDEV_FORMAT_TRY);
919                 switch (code->index) {
920                 case 0:
921                         /* Passthrough sink pad code */
922                         code->code = format->code;
923                         break;
924                 case 1:
925                         /* Uncompressed code */
926                         info = omap4iss_video_format_info(format->code);
927                         if (info->uncompressed == format->code)
928                                 return -EINVAL;
929
930                         code->code = info->uncompressed;
931                         break;
932                 default:
933                         return -EINVAL;
934                 }
935         }
936
937         return 0;
938 }
939
940 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
941                                 struct v4l2_subdev_fh *fh,
942                                 struct v4l2_subdev_frame_size_enum *fse)
943 {
944         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
945         struct v4l2_mbus_framefmt format;
946
947         if (fse->index != 0)
948                 return -EINVAL;
949
950         format.code = fse->code;
951         format.width = 1;
952         format.height = 1;
953         csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
954         fse->min_width = format.width;
955         fse->min_height = format.height;
956
957         if (format.code != fse->code)
958                 return -EINVAL;
959
960         format.code = fse->code;
961         format.width = -1;
962         format.height = -1;
963         csi2_try_format(csi2, fh, fse->pad, &format, V4L2_SUBDEV_FORMAT_TRY);
964         fse->max_width = format.width;
965         fse->max_height = format.height;
966
967         return 0;
968 }
969
970 /*
971  * csi2_get_format - Handle get format by pads subdev method
972  * @sd : pointer to v4l2 subdev structure
973  * @fh : V4L2 subdev file handle
974  * @fmt: pointer to v4l2 subdev format structure
975  * return -EINVAL or zero on success
976  */
977 static int csi2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
978                            struct v4l2_subdev_format *fmt)
979 {
980         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
981         struct v4l2_mbus_framefmt *format;
982
983         format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
984         if (format == NULL)
985                 return -EINVAL;
986
987         fmt->format = *format;
988         return 0;
989 }
990
991 /*
992  * csi2_set_format - Handle set format by pads subdev method
993  * @sd : pointer to v4l2 subdev structure
994  * @fh : V4L2 subdev file handle
995  * @fmt: pointer to v4l2 subdev format structure
996  * return -EINVAL or zero on success
997  */
998 static int csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
999                            struct v4l2_subdev_format *fmt)
1000 {
1001         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1002         struct v4l2_mbus_framefmt *format;
1003
1004         format = __csi2_get_format(csi2, fh, fmt->pad, fmt->which);
1005         if (format == NULL)
1006                 return -EINVAL;
1007
1008         csi2_try_format(csi2, fh, fmt->pad, &fmt->format, fmt->which);
1009         *format = fmt->format;
1010
1011         /* Propagate the format from sink to source */
1012         if (fmt->pad == CSI2_PAD_SINK) {
1013                 format = __csi2_get_format(csi2, fh, CSI2_PAD_SOURCE,
1014                                            fmt->which);
1015                 *format = fmt->format;
1016                 csi2_try_format(csi2, fh, CSI2_PAD_SOURCE, format, fmt->which);
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
1023                               struct v4l2_subdev_format *source_fmt,
1024                               struct v4l2_subdev_format *sink_fmt)
1025 {
1026         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1027         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1028         int rval;
1029
1030         pipe->external = media_entity_to_v4l2_subdev(link->source->entity);
1031         rval = omap4iss_get_external_info(pipe, link);
1032         if (rval < 0)
1033                 return rval;
1034
1035         return v4l2_subdev_link_validate_default(sd, link, source_fmt,
1036                                                  sink_fmt);
1037 }
1038
1039 /*
1040  * csi2_init_formats - Initialize formats on all pads
1041  * @sd: ISS CSI2 V4L2 subdevice
1042  * @fh: V4L2 subdev file handle
1043  *
1044  * Initialize all pad formats with default values. If fh is not NULL, try
1045  * formats are initialized on the file handle. Otherwise active formats are
1046  * initialized on the device.
1047  */
1048 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1049 {
1050         struct v4l2_subdev_format format;
1051
1052         memset(&format, 0, sizeof(format));
1053         format.pad = CSI2_PAD_SINK;
1054         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1055         format.format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
1056         format.format.width = 4096;
1057         format.format.height = 4096;
1058         csi2_set_format(sd, fh, &format);
1059
1060         return 0;
1061 }
1062
1063 /*
1064  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1065  * @sd: ISS CSI2 V4L2 subdevice
1066  * @enable: ISS pipeline stream state
1067  *
1068  * Return 0 on success or a negative error code otherwise.
1069  */
1070 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1071 {
1072         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1073         struct iss_device *iss = csi2->iss;
1074         struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1075         struct iss_video *video_out = &csi2->video_out;
1076
1077         if (csi2->state == ISS_PIPELINE_STREAM_STOPPED) {
1078                 if (enable == ISS_PIPELINE_STREAM_STOPPED)
1079                         return 0;
1080
1081                 if (csi2 == &iss->csi2a)
1082                         omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_CSI2_A);
1083                 else if (csi2 == &iss->csi2b)
1084                         omap4iss_subclk_enable(iss, OMAP4_ISS_SUBCLK_CSI2_B);
1085         }
1086
1087         switch (enable) {
1088         case ISS_PIPELINE_STREAM_CONTINUOUS: {
1089                 int ret;
1090
1091                 ret = omap4iss_csiphy_config(iss, sd);
1092                 if (ret < 0)
1093                         return ret;
1094
1095                 if (omap4iss_csiphy_acquire(csi2->phy) < 0)
1096                         return -ENODEV;
1097                 csi2->use_fs_irq = pipe->do_propagation;
1098                 csi2_configure(csi2);
1099                 csi2_print_status(csi2);
1100
1101                 /*
1102                  * When outputting to memory with no buffer available, let the
1103                  * buffer queue handler start the hardware. A DMA queue flag
1104                  * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1105                  * a buffer available.
1106                  */
1107                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1108                     !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
1109                         break;
1110                 /* Enable context 0 and IRQs */
1111                 atomic_set(&csi2->stopping, 0);
1112                 csi2_ctx_enable(csi2, 0, 1);
1113                 csi2_if_enable(csi2, 1);
1114                 iss_video_dmaqueue_flags_clr(video_out);
1115                 break;
1116         }
1117         case ISS_PIPELINE_STREAM_STOPPED:
1118                 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED)
1119                         return 0;
1120                 if (omap4iss_module_sync_idle(&sd->entity, &csi2->wait,
1121                                               &csi2->stopping))
1122                         dev_dbg(iss->dev, "%s: module stop timeout.\n",
1123                                 sd->name);
1124                 csi2_ctx_enable(csi2, 0, 0);
1125                 csi2_if_enable(csi2, 0);
1126                 csi2_irq_ctx_set(csi2, 0);
1127                 omap4iss_csiphy_release(csi2->phy);
1128                 if (csi2 == &iss->csi2a)
1129                         omap4iss_subclk_disable(iss, OMAP4_ISS_SUBCLK_CSI2_A);
1130                 else if (csi2 == &iss->csi2b)
1131                         omap4iss_subclk_disable(iss, OMAP4_ISS_SUBCLK_CSI2_B);
1132                 iss_video_dmaqueue_flags_clr(video_out);
1133                 break;
1134         }
1135
1136         csi2->state = enable;
1137         return 0;
1138 }
1139
1140 /* subdev video operations */
1141 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1142         .s_stream = csi2_set_stream,
1143 };
1144
1145 /* subdev pad operations */
1146 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1147         .enum_mbus_code = csi2_enum_mbus_code,
1148         .enum_frame_size = csi2_enum_frame_size,
1149         .get_fmt = csi2_get_format,
1150         .set_fmt = csi2_set_format,
1151         .link_validate = csi2_link_validate,
1152 };
1153
1154 /* subdev operations */
1155 static const struct v4l2_subdev_ops csi2_ops = {
1156         .video = &csi2_video_ops,
1157         .pad = &csi2_pad_ops,
1158 };
1159
1160 /* subdev internal operations */
1161 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1162         .open = csi2_init_formats,
1163 };
1164
1165 /* -----------------------------------------------------------------------------
1166  * Media entity operations
1167  */
1168
1169 /*
1170  * csi2_link_setup - Setup CSI2 connections.
1171  * @entity : Pointer to media entity structure
1172  * @local  : Pointer to local pad array
1173  * @remote : Pointer to remote pad array
1174  * @flags  : Link flags
1175  * return -EINVAL or zero on success
1176  */
1177 static int csi2_link_setup(struct media_entity *entity,
1178                            const struct media_pad *local,
1179                            const struct media_pad *remote, u32 flags)
1180 {
1181         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1182         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1183         struct iss_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1184
1185         /*
1186          * The ISS core doesn't support pipelines with multiple video outputs.
1187          * Revisit this when it will be implemented, and return -EBUSY for now.
1188          */
1189
1190         switch (local->index | media_entity_type(remote->entity)) {
1191         case CSI2_PAD_SOURCE | MEDIA_ENT_T_DEVNODE:
1192                 if (flags & MEDIA_LNK_FL_ENABLED) {
1193                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1194                                 return -EBUSY;
1195                         csi2->output |= CSI2_OUTPUT_MEMORY;
1196                 } else {
1197                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1198                 }
1199                 break;
1200
1201         case CSI2_PAD_SOURCE | MEDIA_ENT_T_V4L2_SUBDEV:
1202                 if (flags & MEDIA_LNK_FL_ENABLED) {
1203                         if (csi2->output & ~CSI2_OUTPUT_IPIPEIF)
1204                                 return -EBUSY;
1205                         csi2->output |= CSI2_OUTPUT_IPIPEIF;
1206                 } else {
1207                         csi2->output &= ~CSI2_OUTPUT_IPIPEIF;
1208                 }
1209                 break;
1210
1211         default:
1212                 /* Link from camera to CSI2 is fixed... */
1213                 return -EINVAL;
1214         }
1215
1216         ctrl->vp_only_enable =
1217                 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1218         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
1219
1220         return 0;
1221 }
1222
1223 /* media operations */
1224 static const struct media_entity_operations csi2_media_ops = {
1225         .link_setup = csi2_link_setup,
1226         .link_validate = v4l2_subdev_link_validate,
1227 };
1228
1229 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2)
1230 {
1231         v4l2_device_unregister_subdev(&csi2->subdev);
1232         omap4iss_video_unregister(&csi2->video_out);
1233 }
1234
1235 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
1236                                     struct v4l2_device *vdev)
1237 {
1238         int ret;
1239
1240         /* Register the subdev and video nodes. */
1241         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1242         if (ret < 0)
1243                 goto error;
1244
1245         ret = omap4iss_video_register(&csi2->video_out, vdev);
1246         if (ret < 0)
1247                 goto error;
1248
1249         return 0;
1250
1251 error:
1252         omap4iss_csi2_unregister_entities(csi2);
1253         return ret;
1254 }
1255
1256 /* -----------------------------------------------------------------------------
1257  * ISS CSI2 initialisation and cleanup
1258  */
1259
1260 /*
1261  * csi2_init_entities - Initialize subdev and media entity.
1262  * @csi2: Pointer to csi2 structure.
1263  * return -ENOMEM or zero on success
1264  */
1265 static int csi2_init_entities(struct iss_csi2_device *csi2, const char *subname)
1266 {
1267         struct v4l2_subdev *sd = &csi2->subdev;
1268         struct media_pad *pads = csi2->pads;
1269         struct media_entity *me = &sd->entity;
1270         int ret;
1271         char name[V4L2_SUBDEV_NAME_SIZE];
1272
1273         v4l2_subdev_init(sd, &csi2_ops);
1274         sd->internal_ops = &csi2_internal_ops;
1275         sprintf(name, "CSI2%s", subname);
1276         strlcpy(sd->name, "", sizeof(sd->name));
1277         sprintf(sd->name, "OMAP4 ISS %s", name);
1278
1279         sd->grp_id = 1 << 16;   /* group ID for iss subdevs */
1280         v4l2_set_subdevdata(sd, csi2);
1281         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1282
1283         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1284         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1285
1286         me->ops = &csi2_media_ops;
1287         ret = media_entity_init(me, CSI2_PADS_NUM, pads, 0);
1288         if (ret < 0)
1289                 return ret;
1290
1291         csi2_init_formats(sd, NULL);
1292
1293         /* Video device node */
1294         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1295         csi2->video_out.ops = &csi2_issvideo_ops;
1296         csi2->video_out.bpl_alignment = 32;
1297         csi2->video_out.bpl_zero_padding = 1;
1298         csi2->video_out.bpl_max = 0x1ffe0;
1299         csi2->video_out.iss = csi2->iss;
1300         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1301
1302         ret = omap4iss_video_init(&csi2->video_out, name);
1303         if (ret < 0)
1304                 goto error_video;
1305
1306         /* Connect the CSI2 subdev to the video node. */
1307         ret = media_entity_create_link(&csi2->subdev.entity, CSI2_PAD_SOURCE,
1308                                        &csi2->video_out.video.entity, 0, 0);
1309         if (ret < 0)
1310                 goto error_link;
1311
1312         return 0;
1313
1314 error_link:
1315         omap4iss_video_cleanup(&csi2->video_out);
1316 error_video:
1317         media_entity_cleanup(&csi2->subdev.entity);
1318         return ret;
1319 }
1320
1321 /*
1322  * omap4iss_csi2_init - Routine for module driver init
1323  */
1324 int omap4iss_csi2_init(struct iss_device *iss)
1325 {
1326         struct iss_csi2_device *csi2a = &iss->csi2a;
1327         struct iss_csi2_device *csi2b = &iss->csi2b;
1328         int ret;
1329
1330         csi2a->iss = iss;
1331         csi2a->available = 1;
1332         csi2a->regs1 = iss->regs[OMAP4_ISS_MEM_CSI2_A_REGS1];
1333         csi2a->phy = &iss->csiphy1;
1334         csi2a->state = ISS_PIPELINE_STREAM_STOPPED;
1335         init_waitqueue_head(&csi2a->wait);
1336
1337         ret = csi2_init_entities(csi2a, "a");
1338         if (ret < 0)
1339                 return ret;
1340
1341         csi2b->iss = iss;
1342         csi2b->available = 1;
1343         csi2b->regs1 = iss->regs[OMAP4_ISS_MEM_CSI2_B_REGS1];
1344         csi2b->phy = &iss->csiphy2;
1345         csi2b->state = ISS_PIPELINE_STREAM_STOPPED;
1346         init_waitqueue_head(&csi2b->wait);
1347
1348         ret = csi2_init_entities(csi2b, "b");
1349         if (ret < 0)
1350                 return ret;
1351
1352         return 0;
1353 }
1354
1355 /*
1356  * omap4iss_csi2_cleanup - Routine for module driver cleanup
1357  */
1358 void omap4iss_csi2_cleanup(struct iss_device *iss)
1359 {
1360         struct iss_csi2_device *csi2a = &iss->csi2a;
1361         struct iss_csi2_device *csi2b = &iss->csi2b;
1362
1363         omap4iss_video_cleanup(&csi2a->video_out);
1364         media_entity_cleanup(&csi2a->subdev.entity);
1365
1366         omap4iss_video_cleanup(&csi2b->video_out);
1367         media_entity_cleanup(&csi2b->subdev.entity);
1368 }