OMAP4: clock: DPLL cascading cannot invoke CPUfreq
authorMike Turquette <mturquette@ti.com>
Thu, 19 May 2011 21:39:32 +0000 (16:39 -0500)
committerPraneeth Bajjuri <praneeth@ti.com>
Sat, 21 May 2011 00:32:22 +0000 (19:32 -0500)
commit3fe202bcdced848144bfcad91242d2629a44840b
treeb10dc4e0dadab087dc4f497a3089bb9652d2d651
parentfabdd9fd1398c2a32e2e3ec6e6faf6c5128d5880
OMAP4: clock: DPLL cascading cannot invoke CPUfreq

CPUfreq interfaces were used for controlling DPLL_MPU within DPLL cascading,
but this causes some race conditions in voltage layer/SmartReflex layer due
to competing calls to change voltages.

Instead, set DPLL_MPU clock rate via clock framework APIs so that only one
set of smart_reflex_enable/disable calls happen during DPLL cascading
sequence.

TODO: handle MPU local timer calibration from clock framework notifers
instead of from CPUfreq notifiers.

Change-Id: I38a6592878ae8f1e53aba0c8a06d1cadebb4cf30
Signed-off-by: Mike Turquette <mturquette@ti.com>
arch/arm/kernel/smp_twd.c
arch/arm/mach-omap2/dpll-44xx.c