OMAP4: SR: handle SRCLKLENGTH for DPLL cascading

OMAP4: SR: handle SRCLKLENGTH for DPLL cascading

In DPLL cascading mode SYS_CLK is gated.  This impacts many IP, including
the SmartReflex AVS modules.  To compensate for loss of SYS_CLK the
SR_xxx_SYSCLK clocks derived from the PRM use the 32K timer as a clock
source.  As such the SRCLKLENGTH value needs to be updated for this change
in frequency.  In DPLL cascading the rate of this clock should be 12.288MHz.

This patch implements three distinct changes:

1) handle SR transitions in DPLL cascading code.  This means wrapping DPLL
   frequency changes with SR enable/disable calls.
2) add a 12.288MHz option to the existing sr_set_clk_length function and
   give it the ability to detect whether we are in DPLL cascading mode or
   not.
3) Remove optimizations in sr_configure_errgen and sr_configure_minmax to
   skip sr_set_clk_length re-calibration if the clk_length parameter exists.
   The assumption was that this value would never change after initial
   calibration at boot; that assumption fails in light of DPLL cascading
   scenario.

Change-Id: I93672ccb8d89266595b2b1cff3ec43e83806e8db
Signed-off-by: Mike Turquette <mturquette@ti.com>