omap4iss: csiphy: Fix break on cpu_is_xxxx
[omap4-v4l2-camera:sandusandus-sandusandus-omap4-v4l2-camera.git] / drivers / media / video / omap4iss / iss_csiphy.c
1 /*
2  * TI OMAP4 ISS V4L2 Driver - CSI PHY module
3  *
4  * Copyright (C) 2012 Texas Instruments, Inc.
5  *
6  * Author: Sergio Aguirre <saaguirre@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/delay.h>
15 #include <linux/device.h>
16
17 #include <plat/cpu.h>
18
19 #include "../../../../arch/arm/mach-omap2/control.h"
20
21 #include "iss.h"
22 #include "iss_regs.h"
23 #include "iss_csiphy.h"
24
25 /*
26  * csiphy_lanes_config - Configuration of CSIPHY lanes.
27  *
28  * Updates HW configuration.
29  * Called with phy->mutex taken.
30  */
31 static void csiphy_lanes_config(struct iss_csiphy *phy)
32 {
33         unsigned int i;
34         u32 reg;
35
36         reg = readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG);
37
38         for (i = 0; i < phy->max_data_lanes; i++) {
39                 reg &= ~(CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) |
40                          CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i + 1));
41                 reg |= (phy->lanes.data[i].pol ?
42                         CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) : 0);
43                 reg |= (phy->lanes.data[i].pos <<
44                         CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i + 1));
45         }
46
47         reg &= ~(CSI2_COMPLEXIO_CFG_CLOCK_POL |
48                  CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK);
49         reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;
50         reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;
51
52         writel(reg, phy->cfg_regs + CSI2_COMPLEXIO_CFG);
53 }
54
55 /*
56  * csiphy_set_power
57  * @power: Power state to be set.
58  *
59  * Returns 0 if successful, or -EBUSY if the retry count is exceeded.
60  */
61 static int csiphy_set_power(struct iss_csiphy *phy, u32 power)
62 {
63         u32 reg;
64         u8 retry_count;
65
66         writel((readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG) &
67                 ~CSI2_COMPLEXIO_CFG_PWD_CMD_MASK) |
68                 power,
69                 phy->cfg_regs + CSI2_COMPLEXIO_CFG);
70
71         retry_count = 0;
72         do {
73                 udelay(1);
74                 reg = readl(phy->cfg_regs + CSI2_COMPLEXIO_CFG) &
75                                 CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK;
76
77                 if (reg != power >> 2)
78                         retry_count++;
79
80         } while ((reg != power >> 2) && (retry_count < 100));
81
82         if (retry_count == 100) {
83                 printk(KERN_ERR "CSI2 CIO set power failed!\n");
84                 return -EBUSY;
85         }
86
87         return 0;
88 }
89
90 /*
91  * csiphy_dphy_config - Configure CSI2 D-PHY parameters.
92  *
93  * Called with phy->mutex taken.
94  */
95 static void csiphy_dphy_config(struct iss_csiphy *phy)
96 {
97         u32 reg;
98
99         /* Set up REGISTER0 */
100         reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT;
101         reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT;
102
103         writel(reg, phy->phy_regs + REGISTER0);
104
105         /* Set up REGISTER1 */
106         reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT;
107         reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT;
108         reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT;
109         reg |= 0xB8 << REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT;
110
111         writel(reg, phy->phy_regs + REGISTER1);
112 }
113
114 /*
115  * TCLK values are OK at their reset values
116  */
117 #define TCLK_TERM       0
118 #define TCLK_MISS       1
119 #define TCLK_SETTLE     14
120
121 int omap4iss_csiphy_config(struct iss_device *iss,
122                            struct v4l2_subdev *csi2_subdev)
123 {
124         struct iss_csi2_device *csi2 = v4l2_get_subdevdata(csi2_subdev);
125         struct iss_pipeline *pipe = to_iss_pipeline(&csi2_subdev->entity);
126         struct iss_v4l2_subdevs_group *subdevs = pipe->external->host_priv;
127         struct iss_csiphy_dphy_cfg csi2phy;
128         int csi2_ddrclk_khz;
129         struct iss_csiphy_lanes_cfg *lanes;
130         unsigned int used_lanes = 0;
131         unsigned int i;
132
133         lanes = &subdevs->bus.csi2.lanecfg;
134
135         if (cpu_is_omap44xx()) {
136                 u32 cam_rx_ctrl = omap4_ctrl_pad_readl(
137                                 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);
138
139                 /*
140                  * SCM.CONTROL_CAMERA_RX
141                  * - bit [31] : CSIPHY2 lane 2 enable (4460+ only)
142                  * - bit [30:29] : CSIPHY2 per-lane enable (1 to 0)
143                  * - bit [28:24] : CSIPHY1 per-lane enable (4 to 0)
144                  * - bit [21] : CSIPHY2 CTRLCLK enable
145                  * - bit [20:19] : CSIPHY2 config: 00 d-phy, 01/10 ccp2
146                  * - bit [18] : CSIPHY1 CTRLCLK enable
147                  * - bit [17:16] : CSIPHY1 config: 00 d-phy, 01/10 ccp2
148                  */
149
150                 if (subdevs->interface == ISS_INTERFACE_CSI2A_PHY1) {
151                         cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI21_LANEENABLE_MASK |
152                                         OMAP4_CAMERARX_CSI21_CAMMODE_MASK);
153                         /* NOTE: Leave CSIPHY1 config to 0x0: D-PHY mode */
154                         /* Enable all lanes for now */
155                         cam_rx_ctrl |=
156                                 0x7 << OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT;
157                         /* Enable CTRLCLK */
158                         cam_rx_ctrl |= OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK;
159                 }
160
161                 if (subdevs->interface == ISS_INTERFACE_CSI2B_PHY2) {
162                         cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI22_LANEENABLE_MASK |
163                                         OMAP4_CAMERARX_CSI22_CAMMODE_MASK);
164                         /* NOTE: Leave CSIPHY2 config to 0x0: D-PHY mode */
165                         /* Enable all lanes for now */
166                         cam_rx_ctrl |=
167                                 0x3 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT;
168                         /* Enable CTRLCLK */
169                         cam_rx_ctrl |= OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK;
170                 }
171
172                 omap4_ctrl_pad_writel(cam_rx_ctrl,
173                          OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX);
174         }
175
176         /* Reset used lane count */
177         csi2->phy->used_data_lanes = 0;
178
179         /* Clock and data lanes verification */
180         for (i = 0; i < csi2->phy->max_data_lanes; i++) {
181                 if (lanes->data[i].pos == 0)
182                         continue;
183
184                 if (lanes->data[i].pol > 1 || lanes->data[i].pos > (csi2->phy->max_data_lanes + 1))
185                         return -EINVAL;
186
187                 if (used_lanes & (1 << lanes->data[i].pos))
188                         return -EINVAL;
189
190                 used_lanes |= 1 << lanes->data[i].pos;
191                 csi2->phy->used_data_lanes++;
192         }
193
194         if (lanes->clk.pol > 1 || lanes->clk.pos > (csi2->phy->max_data_lanes + 1))
195                 return -EINVAL;
196
197         if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
198                 return -EINVAL;
199
200         csi2_ddrclk_khz = pipe->external_rate / 1000
201                 / (2 * csi2->phy->used_data_lanes)
202                 * pipe->external_bpp;
203
204         /*
205          * THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1.
206          * THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3.
207          */
208         csi2phy.ths_term = DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1;
209         csi2phy.ths_settle = DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3;
210         csi2phy.tclk_term = TCLK_TERM;
211         csi2phy.tclk_miss = TCLK_MISS;
212         csi2phy.tclk_settle = TCLK_SETTLE;
213
214         mutex_lock(&csi2->phy->mutex);
215         csi2->phy->dphy = csi2phy;
216         csi2->phy->lanes = *lanes;
217         mutex_unlock(&csi2->phy->mutex);
218
219         return 0;
220 }
221
222 int omap4iss_csiphy_acquire(struct iss_csiphy *phy)
223 {
224         int rval;
225
226         mutex_lock(&phy->mutex);
227
228         rval = omap4iss_csi2_reset(phy->csi2);
229         if (rval)
230                 goto done;
231
232         csiphy_dphy_config(phy);
233         csiphy_lanes_config(phy);
234
235         rval = csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_ON);
236         if (rval)
237                 goto done;
238
239         phy->phy_in_use = 1;
240
241 done:
242         mutex_unlock(&phy->mutex);
243         return rval;
244 }
245
246 void omap4iss_csiphy_release(struct iss_csiphy *phy)
247 {
248         mutex_lock(&phy->mutex);
249         if (phy->phy_in_use) {
250                 csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_OFF);
251                 phy->phy_in_use = 0;
252         }
253         mutex_unlock(&phy->mutex);
254 }
255
256 /*
257  * omap4iss_csiphy_init - Initialize the CSI PHY frontends
258  */
259 int omap4iss_csiphy_init(struct iss_device *iss)
260 {
261         struct iss_csiphy *phy1 = &iss->csiphy1;
262         struct iss_csiphy *phy2 = &iss->csiphy2;
263
264         phy1->iss = iss;
265         phy1->csi2 = &iss->csi2a;
266         phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES;
267         phy1->used_data_lanes = 0;
268         phy1->cfg_regs = iss->regs[OMAP4_ISS_MEM_CSI2_A_REGS1];
269         phy1->phy_regs = iss->regs[OMAP4_ISS_MEM_CAMERARX_CORE1];
270         mutex_init(&phy1->mutex);
271
272         phy2->iss = iss;
273         phy2->csi2 = &iss->csi2b;
274         phy2->max_data_lanes = ISS_CSIPHY2_NUM_DATA_LANES;
275         phy2->used_data_lanes = 0;
276         phy2->cfg_regs = iss->regs[OMAP4_ISS_MEM_CSI2_B_REGS1];
277         phy2->phy_regs = iss->regs[OMAP4_ISS_MEM_CAMERARX_CORE2];
278         mutex_init(&phy2->mutex);
279
280         return 0;
281 }