omap4iss: Add initial support for resizer block
[omap4-v4l2-camera:xmd1983s-omap4-v4l2-camera.git] / drivers / media / video / omap4iss / iss_regs.h
1 /*
2  * TI OMAP4 ISS V4L2 Driver - Register defines
3  *
4  * Copyright (C) 2012 Texas Instruments.
5  *
6  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #ifndef _OMAP4_ISS_REGS_H_
15 #define _OMAP4_ISS_REGS_H_
16
17 /* ISS */
18 #define ISS_HL_REVISION                                 0x0
19
20 #define ISS_HL_SYSCONFIG                                0x10
21 #define ISS_HL_SYSCONFIG_IDLEMODE_SHIFT                 2
22 #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE             0x0
23 #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE                0x1
24 #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE             0x2
25 #define ISS_HL_SYSCONFIG_SOFTRESET                      (1 << 0)
26
27 #define ISS_HL_IRQSTATUS_5                              (0x24 + (0x10 * 5))
28 #define ISS_HL_IRQENABLE_5_SET                          (0x28 + (0x10 * 5))
29 #define ISS_HL_IRQENABLE_5_CLR                          (0x2C + (0x10 * 5))
30
31 #define ISS_HL_IRQ_BTE                                  (1 << 11)
32 #define ISS_HL_IRQ_CBUFF                                (1 << 10)
33 #define ISS_HL_IRQ_CSIB                                 (1 << 5)
34 #define ISS_HL_IRQ_CSIA                                 (1 << 4)
35 #define ISS_HL_IRQ_ISP(i)                               (1 << (i))
36
37 #define ISS_CTRL                                        0x80
38 #define ISS_CTRL_CLK_DIV_MASK                           (3 << 4)
39 #define ISS_CTRL_INPUT_SEL_MASK                         (3 << 2)
40 #define ISS_CTRL_INPUT_SEL_CSI2A                        (0 << 2)
41 #define ISS_CTRL_INPUT_SEL_CSI2B                        (1 << 2)
42 #define ISS_CTRL_SYNC_DETECT_VS_RAISING                 (3 << 0)
43
44 #define ISS_CLKCTRL                                     0x84
45 #define ISS_CLKCTRL_VPORT2_CLK                          (1 << 30)
46 #define ISS_CLKCTRL_VPORT1_CLK                          (1 << 29)
47 #define ISS_CLKCTRL_VPORT0_CLK                          (1 << 28)
48 #define ISS_CLKCTRL_CCP2                                (1 << 4)
49 #define ISS_CLKCTRL_CSI2_B                              (1 << 3)
50 #define ISS_CLKCTRL_CSI2_A                              (1 << 2)
51 #define ISS_CLKCTRL_ISP                                 (1 << 1)
52 #define ISS_CLKCTRL_SIMCOP                              (1 << 0)
53
54 #define ISS_CLKSTAT                                     0x88
55 #define ISS_CLKSTAT_VPORT2_CLK                          (1 << 30)
56 #define ISS_CLKSTAT_VPORT1_CLK                          (1 << 29)
57 #define ISS_CLKSTAT_VPORT0_CLK                          (1 << 28)
58 #define ISS_CLKSTAT_CCP2                                (1 << 4)
59 #define ISS_CLKSTAT_CSI2_B                              (1 << 3)
60 #define ISS_CLKSTAT_CSI2_A                              (1 << 2)
61 #define ISS_CLKSTAT_ISP                                 (1 << 1)
62 #define ISS_CLKSTAT_SIMCOP                              (1 << 0)
63
64 #define ISS_PM_STATUS                                   0x8C
65 #define ISS_PM_STATUS_CBUFF_PM_MASK                     (3 << 12)
66 #define ISS_PM_STATUS_BTE_PM_MASK                       (3 << 10)
67 #define ISS_PM_STATUS_SIMCOP_PM_MASK                    (3 << 8)
68 #define ISS_PM_STATUS_ISP_PM_MASK                       (3 << 6)
69 #define ISS_PM_STATUS_CCP2_PM_MASK                      (3 << 4)
70 #define ISS_PM_STATUS_CSI2_B_PM_MASK                    (3 << 2)
71 #define ISS_PM_STATUS_CSI2_A_PM_MASK                    (3 << 0)
72
73 #define REGISTER0                                       0x0
74 #define REGISTER0_HSCLOCKCONFIG                         (1 << 24)
75 #define REGISTER0_THS_TERM_MASK                         (0xFF << 8)
76 #define REGISTER0_THS_TERM_SHIFT                        8
77 #define REGISTER0_THS_SETTLE_MASK                       (0xFF << 0)
78 #define REGISTER0_THS_SETTLE_SHIFT                      0
79
80 #define REGISTER1                                       0x4
81 #define REGISTER1_RESET_DONE_CTRLCLK                    (1 << 29)
82 #define REGISTER1_CLOCK_MISS_DETECTOR_STATUS            (1 << 25)
83 #define REGISTER1_TCLK_TERM_MASK                        (0x3F << 18)
84 #define REGISTER1_TCLK_TERM_SHIFT                       18
85 #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT            10
86 #define REGISTER1_CTRLCLK_DIV_FACTOR_MASK               (0x3 << 8)
87 #define REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT              8
88 #define REGISTER1_TCLK_SETTLE_MASK                      (0xFF << 0)
89 #define REGISTER1_TCLK_SETTLE_SHIFT                     0
90
91 #define REGISTER2                                       0x8
92
93 #define CSI2_SYSCONFIG                                  0x10
94 #define CSI2_SYSCONFIG_MSTANDBY_MODE_MASK               (3 << 12)
95 #define CSI2_SYSCONFIG_MSTANDBY_MODE_FORCE              (0 << 12)
96 #define CSI2_SYSCONFIG_MSTANDBY_MODE_NO                 (1 << 12)
97 #define CSI2_SYSCONFIG_MSTANDBY_MODE_SMART              (2 << 12)
98 #define CSI2_SYSCONFIG_SOFT_RESET                       (1 << 1)
99 #define CSI2_SYSCONFIG_AUTO_IDLE                        (1 << 0)
100
101 #define CSI2_SYSSTATUS                                  0x14
102 #define CSI2_SYSSTATUS_RESET_DONE                       (1 << 0)
103
104 #define CSI2_IRQSTATUS                                  0x18
105 #define CSI2_IRQENABLE                                  0x1C
106
107 /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */
108
109 #define CSI2_IRQ_OCP_ERR                                (1 << 14)
110 #define CSI2_IRQ_SHORT_PACKET                           (1 << 13)
111 #define CSI2_IRQ_ECC_CORRECTION                         (1 << 12)
112 #define CSI2_IRQ_ECC_NO_CORRECTION                      (1 << 11)
113 #define CSI2_IRQ_COMPLEXIO_ERR                          (1 << 9)
114 #define CSI2_IRQ_FIFO_OVF                               (1 << 8)
115 #define CSI2_IRQ_CONTEXT0                               (1 << 0)
116
117 #define CSI2_CTRL                                       0x40
118 #define CSI2_CTRL_MFLAG_LEVH_MASK                       (7 << 20)
119 #define CSI2_CTRL_MFLAG_LEVH_SHIFT                      20
120 #define CSI2_CTRL_MFLAG_LEVL_MASK                       (7 << 17)
121 #define CSI2_CTRL_MFLAG_LEVL_SHIFT                      17
122 #define CSI2_CTRL_BURST_SIZE_EXPAND                     (1 << 16)
123 #define CSI2_CTRL_VP_CLK_EN                             (1 << 15)
124 #define CSI2_CTRL_NON_POSTED_WRITE                      (1 << 13)
125 #define CSI2_CTRL_VP_ONLY_EN                            (1 << 11)
126 #define CSI2_CTRL_VP_OUT_CTRL_MASK                      (3 << 8)
127 #define CSI2_CTRL_VP_OUT_CTRL_SHIFT                     8
128 #define CSI2_CTRL_DBG_EN                                (1 << 7)
129 #define CSI2_CTRL_BURST_SIZE_MASK                       (3 << 5)
130 #define CSI2_CTRL_ENDIANNESS                            (1 << 4)
131 #define CSI2_CTRL_FRAME                                 (1 << 3)
132 #define CSI2_CTRL_ECC_EN                                (1 << 2)
133 #define CSI2_CTRL_IF_EN                                 (1 << 0)
134
135 #define CSI2_DBG_H                                      0x44
136
137 #define CSI2_COMPLEXIO_CFG                              0x50
138 #define CSI2_COMPLEXIO_CFG_RESET_CTRL                   (1 << 30)
139 #define CSI2_COMPLEXIO_CFG_RESET_DONE                   (1 << 29)
140 #define CSI2_COMPLEXIO_CFG_PWD_CMD_MASK                 (3 << 27)
141 #define CSI2_COMPLEXIO_CFG_PWD_CMD_OFF                  (0 << 27)
142 #define CSI2_COMPLEXIO_CFG_PWD_CMD_ON                   (1 << 27)
143 #define CSI2_COMPLEXIO_CFG_PWD_CMD_ULP                  (2 << 27)
144 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK              (3 << 25)
145 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_OFF               (0 << 25)
146 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ON                (1 << 25)
147 #define CSI2_COMPLEXIO_CFG_PWD_STATUS_ULP               (2 << 25)
148 #define CSI2_COMPLEXIO_CFG_PWR_AUTO                     (1 << 24)
149 #define CSI2_COMPLEXIO_CFG_DATA_POL(i)                  (1 << (((i) * 4) + 3))
150 #define CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i)        (7 << ((i) * 4))
151 #define CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i)       ((i) * 4)
152 #define CSI2_COMPLEXIO_CFG_CLOCK_POL                    (1 << 3)
153 #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK          (7 << 0)
154 #define CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT         0
155
156 #define CSI2_COMPLEXIO_IRQSTATUS                        0x54
157
158 #define CSI2_SHORT_PACKET                               0x5C
159
160 #define CSI2_COMPLEXIO_IRQENABLE                        0x60
161
162 /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */
163 #define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT             (1 << 26)
164 #define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER            (1 << 25)
165 #define CSI2_COMPLEXIO_IRQ_STATEULPM5                   (1 << 24)
166 #define CSI2_COMPLEXIO_IRQ_STATEULPM4                   (1 << 23)
167 #define CSI2_COMPLEXIO_IRQ_STATEULPM3                   (1 << 22)
168 #define CSI2_COMPLEXIO_IRQ_STATEULPM2                   (1 << 21)
169 #define CSI2_COMPLEXIO_IRQ_STATEULPM1                   (1 << 20)
170 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL5                  (1 << 19)
171 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL4                  (1 << 18)
172 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL3                  (1 << 17)
173 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL2                  (1 << 16)
174 #define CSI2_COMPLEXIO_IRQ_ERRCONTROL1                  (1 << 15)
175 #define CSI2_COMPLEXIO_IRQ_ERRESC5                      (1 << 14)
176 #define CSI2_COMPLEXIO_IRQ_ERRESC4                      (1 << 13)
177 #define CSI2_COMPLEXIO_IRQ_ERRESC3                      (1 << 12)
178 #define CSI2_COMPLEXIO_IRQ_ERRESC2                      (1 << 11)
179 #define CSI2_COMPLEXIO_IRQ_ERRESC1                      (1 << 10)
180 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5                (1 << 9)
181 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4                (1 << 8)
182 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3                (1 << 7)
183 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2                (1 << 6)
184 #define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1                (1 << 5)
185 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS5                    (1 << 4)
186 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS4                    (1 << 3)
187 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS3                    (1 << 2)
188 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS2                    (1 << 1)
189 #define CSI2_COMPLEXIO_IRQ_ERRSOTHS1                    (1 << 0)
190
191 #define CSI2_DBG_P                                      0x68
192
193 #define CSI2_TIMING                                     0x6C
194 #define CSI2_TIMING_FORCE_RX_MODE_IO1                   (1 << 15)
195 #define CSI2_TIMING_STOP_STATE_X16_IO1                  (1 << 14)
196 #define CSI2_TIMING_STOP_STATE_X4_IO1                   (1 << 13)
197 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK         (0x1FFF << 0)
198 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT        0
199
200 #define CSI2_CTX_CTRL1(i)                               (0x70 + (0x20 * i))
201 #define CSI2_CTX_CTRL1_GENERIC                          (1 << 30)
202 #define CSI2_CTX_CTRL1_TRANSCODE                        (0xF << 24)
203 #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK                  (0xFF << 16)
204 #define CSI2_CTX_CTRL1_COUNT_MASK                       (0xFF << 8)
205 #define CSI2_CTX_CTRL1_COUNT_SHIFT                      8
206 #define CSI2_CTX_CTRL1_EOF_EN                           (1 << 7)
207 #define CSI2_CTX_CTRL1_EOL_EN                           (1 << 6)
208 #define CSI2_CTX_CTRL1_CS_EN                            (1 << 5)
209 #define CSI2_CTX_CTRL1_COUNT_UNLOCK                     (1 << 4)
210 #define CSI2_CTX_CTRL1_PING_PONG                        (1 << 3)
211 #define CSI2_CTX_CTRL1_CTX_EN                           (1 << 0)
212
213 #define CSI2_CTX_CTRL2(i)                               (0x74 + (0x20 * i))
214 #define CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT               13
215 #define CSI2_CTX_CTRL2_USER_DEF_MAP_MASK                \
216                 (0x3 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
217 #define CSI2_CTX_CTRL2_VIRTUAL_ID_MASK                  (3 << 11)
218 #define CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT                 11
219 #define CSI2_CTX_CTRL2_DPCM_PRED                        (1 << 10)
220 #define CSI2_CTX_CTRL2_FORMAT_MASK                      (0x3FF << 0)
221 #define CSI2_CTX_CTRL2_FORMAT_SHIFT                     0
222
223 #define CSI2_CTX_DAT_OFST(i)                            (0x78 + (0x20 * i))
224 #define CSI2_CTX_DAT_OFST_MASK                          (0xFFF << 5)
225
226 #define CSI2_CTX_PING_ADDR(i)                           (0x7C + (0x20 * i))
227 #define CSI2_CTX_PING_ADDR_MASK                         0xFFFFFFE0
228
229 #define CSI2_CTX_PONG_ADDR(i)                           (0x80 + (0x20 * i))
230 #define CSI2_CTX_PONG_ADDR_MASK                         CSI2_CTX_PING_ADDR_MASK
231
232 #define CSI2_CTX_IRQENABLE(i)                           (0x84 + (0x20 * i))
233 #define CSI2_CTX_IRQSTATUS(i)                           (0x88 + (0x20 * i))
234
235 #define CSI2_CTX_CTRL3(i)                               (0x8C + (0x20 * i))
236 #define CSI2_CTX_CTRL3_ALPHA_SHIFT                      5
237 #define CSI2_CTX_CTRL3_ALPHA_MASK                       \
238                 (0x3fff << CSI2_CTX_CTRL3_ALPHA_SHIFT)
239
240 /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */
241 #define CSI2_CTX_IRQ_ECC_CORRECTION                     (1 << 8)
242 #define CSI2_CTX_IRQ_LINE_NUMBER                        (1 << 7)
243 #define CSI2_CTX_IRQ_FRAME_NUMBER                       (1 << 6)
244 #define CSI2_CTX_IRQ_CS                                 (1 << 5)
245 #define CSI2_CTX_IRQ_LE                                 (1 << 3)
246 #define CSI2_CTX_IRQ_LS                                 (1 << 2)
247 #define CSI2_CTX_IRQ_FE                                 (1 << 1)
248 #define CSI2_CTX_IRQ_FS                                 (1 << 0)
249
250 /* ISS ISP_SYS1 */
251 #define ISP5_REVISION                                   (0x0000)
252 #define ISP5_SYSCONFIG                                  (0x0010)
253 #define ISP5_SYSCONFIG_STANDBYMODE_MASK                 (3 << 4)
254 #define ISP5_SYSCONFIG_STANDBYMODE_FORCE                (0 << 4)
255 #define ISP5_SYSCONFIG_STANDBYMODE_NO                   (1 << 4)
256 #define ISP5_SYSCONFIG_STANDBYMODE_SMART                (2 << 4)
257 #define ISP5_SYSCONFIG_SOFTRESET                        (1 << 1)
258
259 #define ISP5_IRQSTATUS(i)                               (0x0028 + (0x10 * (i)))
260 #define ISP5_IRQENABLE_SET(i)                           (0x002C + (0x10 * (i)))
261 #define ISP5_IRQENABLE_CLR(i)                           (0x0030 + (0x10 * (i)))
262
263 /* Bits shared for ISP5_IRQ* registers */
264 #define ISP5_IRQ_OCP_ERR                                (1 << 31)
265 #define ISP5_IRQ_RSZ_INT_EOF0                           (1 << 22)
266 #define ISP5_IRQ_RSZ_FIFO_IN_BLK                        (1 << 19)
267 #define ISP5_IRQ_RSZ_FIFO_OVF                           (1 << 18)
268 #define ISP5_IRQ_RSZ_INT_CYC_RSZA                       (1 << 16)
269 #define ISP5_IRQ_RSZ_INT_DMA                            (1 << 15)
270 #define ISP5_IRQ_IPIPEIF                                (1 << 9)
271 #define ISP5_IRQ_ISIF3                                  (1 << 3)
272 #define ISP5_IRQ_ISIF2                                  (1 << 2)
273 #define ISP5_IRQ_ISIF1                                  (1 << 1)
274 #define ISP5_IRQ_ISIF0                                  (1 << 0)
275
276 #define ISP5_CTRL                                       (0x006C)
277 #define ISP5_CTRL_MSTANDBY                              (1 << 24)
278 #define ISP5_CTRL_VD_PULSE_EXT                          (1 << 23)
279 #define ISP5_CTRL_MSTANDBY_WAIT                         (1 << 20)
280 #define ISP5_CTRL_BL_CLK_ENABLE                         (1 << 15)
281 #define ISP5_CTRL_ISIF_CLK_ENABLE                       (1 << 14)
282 #define ISP5_CTRL_H3A_CLK_ENABLE                        (1 << 13)
283 #define ISP5_CTRL_RSZ_CLK_ENABLE                        (1 << 12)
284 #define ISP5_CTRL_IPIPE_CLK_ENABLE                      (1 << 11)
285 #define ISP5_CTRL_IPIPEIF_CLK_ENABLE                    (1 << 10)
286 #define ISP5_CTRL_SYNC_ENABLE                           (1 << 9)
287 #define ISP5_CTRL_PSYNC_CLK_SEL                         (1 << 8)
288
289 /* ISS ISP ISIF register offsets */
290 #define ISIF_SYNCEN                                     (0x0000)
291 #define ISIF_SYNCEN_DWEN                                (1 << 1)
292 #define ISIF_SYNCEN_SYEN                                (1 << 0)
293
294 #define ISIF_MODESET                                    (0x0004)
295 #define ISIF_MODESET_INPMOD_MASK                        (3 << 12)
296 #define ISIF_MODESET_INPMOD_RAW                         (0 << 12)
297 #define ISIF_MODESET_INPMOD_YCBCR16                     (1 << 12)
298 #define ISIF_MODESET_INPMOD_YCBCR8                      (2 << 12)
299 #define ISIF_MODESET_CCDW_MASK                          (7 << 8)
300 #define ISIF_MODESET_CCDW_2BIT                          (2 << 8)
301 #define ISIF_MODESET_CCDMD                              (1 << 7)
302 #define ISIF_MODESET_SWEN                               (1 << 5)
303 #define ISIF_MODESET_HDPOL                              (1 << 3)
304 #define ISIF_MODESET_VDPOL                              (1 << 2)
305
306 #define ISIF_SPH                                        (0x0018)
307 #define ISIF_SPH_MASK                                   (0x7FFF)
308
309 #define ISIF_LNH                                        (0x001C)
310 #define ISIF_LNH_MASK                                   (0x7FFF)
311
312 #define ISIF_LNV                                        (0x0028)
313 #define ISIF_LNV_MASK                                   (0x7FFF)
314
315 #define ISIF_HSIZE                                      (0x0034)
316 #define ISIF_HSIZE_ADCR                                 (1 << 12)
317 #define ISIF_HSIZE_HSIZE_MASK                           (0xFFF)
318
319 #define ISIF_CADU                                       (0x003C)
320 #define ISIF_CADU_MASK                                  (0x7FF)
321
322 #define ISIF_CADL                                       (0x0040)
323 #define ISIF_CADL_MASK                                  (0xFFFF)
324
325 #define ISIF_CCOLP                                      (0x004C)
326 #define ISIF_CCOLP_CP0_F0_R                             (0 << 6)
327 #define ISIF_CCOLP_CP0_F0_GR                            (1 << 6)
328 #define ISIF_CCOLP_CP0_F0_B                             (3 << 6)
329 #define ISIF_CCOLP_CP0_F0_GB                            (2 << 6)
330 #define ISIF_CCOLP_CP1_F0_R                             (0 << 4)
331 #define ISIF_CCOLP_CP1_F0_GR                            (1 << 4)
332 #define ISIF_CCOLP_CP1_F0_B                             (3 << 4)
333 #define ISIF_CCOLP_CP1_F0_GB                            (2 << 4)
334 #define ISIF_CCOLP_CP2_F0_R                             (0 << 2)
335 #define ISIF_CCOLP_CP2_F0_GR                            (1 << 2)
336 #define ISIF_CCOLP_CP2_F0_B                             (3 << 2)
337 #define ISIF_CCOLP_CP2_F0_GB                            (2 << 2)
338 #define ISIF_CCOLP_CP3_F0_R                             (0 << 0)
339 #define ISIF_CCOLP_CP3_F0_GR                            (1 << 0)
340 #define ISIF_CCOLP_CP3_F0_B                             (3 << 0)
341 #define ISIF_CCOLP_CP3_F0_GB                            (2 << 0)
342
343 #define ISIF_VDINT0                                     (0x0070)
344 #define ISIF_VDINT0_MASK                                (0x7FFF)
345
346 #define ISIF_CGAMMAWD                                   (0x0080)
347 #define ISIF_CGAMMAWD_GWDI_MASK                         (0xF << 1)
348 #define ISIF_CGAMMAWD_GWDI_BIT11                        (0x4 << 1)
349
350 #define ISIF_CCDCFG                                     (0x0088)
351 #define ISIF_CCDCFG_Y8POS                               (1 << 11)
352
353 /* ISS ISP IPIPEIF register offsets */
354 #define IPIPEIF_ENABLE                                  (0x0000)
355
356 #define IPIPEIF_CFG1                                    (0x0004)
357 #define IPIPEIF_CFG1_INPSRC1_MASK                       (3 << 14)
358 #define IPIPEIF_CFG1_INPSRC1_VPORT_RAW                  (0 << 14)
359 #define IPIPEIF_CFG1_INPSRC1_SDRAM_RAW                  (1 << 14)
360 #define IPIPEIF_CFG1_INPSRC1_ISIF_DARKFM                (2 << 14)
361 #define IPIPEIF_CFG1_INPSRC1_SDRAM_YUV                  (3 << 14)
362 #define IPIPEIF_CFG1_INPSRC2_MASK                       (3 << 2)
363 #define IPIPEIF_CFG1_INPSRC2_ISIF                       (0 << 2)
364 #define IPIPEIF_CFG1_INPSRC2_SDRAM_RAW                  (1 << 2)
365 #define IPIPEIF_CFG1_INPSRC2_ISIF_DARKFM                (2 << 2)
366 #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV                  (3 << 2)
367
368 #define IPIPEIF_CFG2                                    (0x0030)
369 #define IPIPEIF_CFG2_YUV8P                              (1 << 7)
370 #define IPIPEIF_CFG2_YUV8                               (1 << 6)
371 #define IPIPEIF_CFG2_YUV16                              (1 << 3)
372 #define IPIPEIF_CFG2_VDPOL                              (1 << 2)
373 #define IPIPEIF_CFG2_HDPOL                              (1 << 1)
374 #define IPIPEIF_CFG2_INTSW                              (1 << 0)
375
376 #define IPIPEIF_CLKDIV                                  (0x0040)
377
378 /* ISS ISP Resizer register offsets */
379 #define RSZ_REVISION                                    (0x0000)
380 #define RSZ_SYSCONFIG                                   (0x0004)
381 #define RSZ_SYSCONFIG_RSZB_CLK_EN                       (1 << 9)
382 #define RSZ_SYSCONFIG_RSZA_CLK_EN                       (1 << 8)
383
384 #define RSZ_IN_FIFO_CTRL                                (0x000C)
385 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK                 (0x1FF << 16)
386 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_SHIFT                16
387 #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_MASK                (0x1FF << 0)
388 #define RSZ_IN_FIFO_CTRL_THRLD_HIGH_SHIFT               0
389
390 #define RSZ_FRACDIV                                     (0x0008)
391 #define RSZ_FRACDIV_MASK                                (0xFFFF)
392
393 #define RSZ_SRC_EN                                      (0x0020)
394 #define RSZ_SRC_EN_SRC_EN                               (1 << 0)
395
396 #define RSZ_SRC_MODE                                    (0x0024)
397 #define RSZ_SRC_MODE_OST                                (1 << 0)
398 #define RSZ_SRC_MODE_WRT                                (1 << 1)
399
400 #define RSZ_SRC_FMT0                                    (0x0028)
401 #define RSZ_SRC_FMT0_BYPASS                             (1 << 1)
402 #define RSZ_SRC_FMT0_SEL                                (1 << 0)
403
404 #define RSZ_SRC_FMT1                                    (0x002C)
405 #define RSZ_SRC_FMT1_IN420                              (1 << 1)
406
407 #define RSZ_SRC_VPS                                     (0x0030)
408 #define RSZ_SRC_VSZ                                     (0x0034)
409 #define RSZ_SRC_HPS                                     (0x0038)
410 #define RSZ_SRC_HSZ                                     (0x003C)
411 #define RSZ_DMA_RZA                                     (0x0040)
412 #define RSZ_DMA_RZB                                     (0x0044)
413 #define RSZ_DMA_STA                                     (0x0048)
414 #define RSZ_GCK_MMR                                     (0x004C)
415 #define RSZ_GCK_MMR_MMR                                 (1 << 0)
416
417 #define RSZ_GCK_SDR                                     (0x0054)
418 #define RSZ_GCK_SDR_CORE                                (1 << 0)
419
420 #define RSZ_IRQ_RZA                                     (0x0058)
421 #define RSZ_IRQ_RZA_MASK                                (0x1FFF)
422
423 #define RSZ_IRQ_RZB                                     (0x005C)
424 #define RSZ_IRQ_RZB_MASK                                (0x1FFF)
425
426 #define RSZ_YUV_Y_MIN                                   (0x0060)
427 #define RSZ_YUV_Y_MAX                                   (0x0064)
428 #define RSZ_YUV_C_MIN                                   (0x0068)
429 #define RSZ_YUV_C_MAX                                   (0x006C)
430
431 #define RSZ_SEQ                                         (0x0074)
432 #define RSZ_SEQ_HRVB                                    (1 << 2)
433 #define RSZ_SEQ_HRVA                                    (1 << 0)
434
435 #define RZA_EN                                          (0x0078)
436 #define RZA_MODE                                        (0x007C)
437 #define RZA_MODE_ONE_SHOT                               (1 << 0)
438
439 #define RZA_420                                         (0x0080)
440 #define RZA_I_VPS                                       (0x0084)
441 #define RZA_I_HPS                                       (0x0088)
442 #define RZA_O_VSZ                                       (0x008C)
443 #define RZA_O_HSZ                                       (0x0090)
444 #define RZA_V_PHS_Y                                     (0x0094)
445 #define RZA_V_PHS_C                                     (0x0098)
446 #define RZA_V_DIF                                       (0x009C)
447 #define RZA_V_TYP                                       (0x00A0)
448 #define RZA_V_LPF                                       (0x00A4)
449 #define RZA_H_PHS                                       (0x00A8)
450 #define RZA_H_DIF                                       (0x00B0)
451 #define RZA_H_TYP                                       (0x00B4)
452 #define RZA_H_LPF                                       (0x00B8)
453 #define RZA_DWN_EN                                      (0x00BC)
454 #define RZA_SDR_Y_BAD_H                                 (0x00D0)
455 #define RZA_SDR_Y_BAD_L                                 (0x00D4)
456 #define RZA_SDR_Y_SAD_H                                 (0x00D8)
457 #define RZA_SDR_Y_SAD_L                                 (0x00DC)
458 #define RZA_SDR_Y_OFT                                   (0x00E0)
459 #define RZA_SDR_Y_PTR_S                                 (0x00E4)
460 #define RZA_SDR_Y_PTR_E                                 (0x00E8)
461 #define RZA_SDR_C_BAD_H                                 (0x00EC)
462 #define RZA_SDR_C_BAD_L                                 (0x00F0)
463 #define RZA_SDR_C_SAD_H                                 (0x00F4)
464 #define RZA_SDR_C_SAD_L                                 (0x00F8)
465 #define RZA_SDR_C_OFT                                   (0x00FC)
466 #define RZA_SDR_C_PTR_S                                 (0x0100)
467 #define RZA_SDR_C_PTR_E                                 (0x0104)
468
469 #define RZB_EN                                          (0x0108)
470 #define RZB_MODE                                        (0x010C)
471 #define RZB_420                                         (0x0110)
472 #define RZB_I_VPS                                       (0x0114)
473 #define RZB_I_HPS                                       (0x0118)
474 #define RZB_O_VSZ                                       (0x011C)
475 #define RZB_O_HSZ                                       (0x0120)
476
477 #define RZB_V_DIF                                       (0x012C)
478 #define RZB_V_TYP                                       (0x0130)
479 #define RZB_V_LPF                                       (0x0134)
480
481 #define RZB_H_DIF                                       (0x0140)
482 #define RZB_H_TYP                                       (0x0144)
483 #define RZB_H_LPF                                       (0x0148)
484
485 #define RZB_SDR_Y_BAD_H                                 (0x0160)
486 #define RZB_SDR_Y_BAD_L                                 (0x0164)
487 #define RZB_SDR_Y_SAD_H                                 (0x0168)
488 #define RZB_SDR_Y_SAD_L                                 (0x016C)
489 #define RZB_SDR_Y_OFT                                   (0x0170)
490 #define RZB_SDR_Y_PTR_S                                 (0x0174)
491 #define RZB_SDR_Y_PTR_E                                 (0x0178)
492 #define RZB_SDR_C_BAD_H                                 (0x017C)
493 #define RZB_SDR_C_BAD_L                                 (0x0180)
494 #define RZB_SDR_C_SAD_H                                 (0x0184)
495 #define RZB_SDR_C_SAD_L                                 (0x0188)
496
497 #define RZB_SDR_C_PTR_S                                 (0x0190)
498 #define RZB_SDR_C_PTR_E                                 (0x0194)
499
500 /* Shared Bitmasks between RZA & RZB */
501 #define RSZ_EN_EN                                       (1 << 0)
502
503 #define RSZ_420_CEN                                     (1 << 1)
504 #define RSZ_420_YEN                                     (1 << 0)
505
506 #define RSZ_I_VPS_MASK                                  (0x1FFF)
507
508 #define RSZ_I_HPS_MASK                                  (0x1FFF)
509
510 #define RSZ_O_VSZ_MASK                                  (0x1FFF)
511
512 #define RSZ_O_HSZ_MASK                                  (0x1FFE)
513
514 #define RSZ_V_PHS_Y_MASK                                (0x3FFF)
515
516 #define RSZ_V_PHS_C_MASK                                (0x3FFF)
517
518 #define RSZ_V_DIF_MASK                                  (0x3FFF)
519
520 #define RSZ_V_TYP_C                                     (1 << 1)
521 #define RSZ_V_TYP_Y                                     (1 << 0)
522
523 #define RSZ_V_LPF_C_MASK                                (0x3F << 6)
524 #define RSZ_V_LPF_C_SHIFT                               6
525 #define RSZ_V_LPF_Y_MASK                                (0x3F << 0)
526 #define RSZ_V_LPF_Y_SHIFT                               0
527
528 #define RSZ_H_PHS_MASK                                  (0x3FFF)
529
530 #define RSZ_H_DIF_MASK                                  (0x3FFF)
531
532 #define RSZ_H_TYP_C                                     (1 << 1)
533 #define RSZ_H_TYP_Y                                     (1 << 0)
534
535 #define RSZ_H_LPF_C_MASK                                (0x3F << 6)
536 #define RSZ_H_LPF_C_SHIFT                               6
537 #define RSZ_H_LPF_Y_MASK                                (0x3F << 0)
538 #define RSZ_H_LPF_Y_SHIFT                               0
539
540 #define RSZ_DWN_EN_DWN_EN                               (1 << 0)
541
542 #endif /* _OMAP4_ISS_REGS_H_ */