[PATCH] 2.5.7 IDE 27
[opensuse:kernel.git] / drivers / ide / hpt366.c
1 /*
2  * linux/drivers/ide/hpt366.c           Version 0.22    20 Sep 2001
3  *
4  * Copyright (C) 1999-2000              Andre Hedrick <andre@linux-ide.org>
5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
6  * May be copied or modified under the terms of the GNU General Public License
7  *
8  * Thanks to HighPoint Technologies for their assistance, and hardware.
9  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10  * donation of an ABit BP6 mainboard, processor, and memory acellerated
11  * development and support.
12  *
13  * Note that final HPT370 support was done by force extraction of GPL.
14  *
15  * - add function for getting/setting power status of drive
16  * - the HPT370's state machine can get confused. reset it before each dma 
17  *   xfer to prevent that from happening.
18  * - reset state engine whenever we get an error.
19  * - check for busmaster state at end of dma. 
20  * - use new highpoint timings.
21  * - detect bus speed using highpoint register.
22  * - use pll if we don't have a clock table. added a 66MHz table that's
23  *   just 2x the 33MHz table.
24  * - removed turnaround. NOTE: we never want to switch between pll and
25  *   pci clocks as the chip can glitch in those cases. the highpoint
26  *   approved workaround slows everything down too much to be useful. in
27  *   addition, we would have to serialize access to each chip.
28  *      Adrian Sun <a.sun@sun.com>
29  *
30  * add drive timings for 66MHz PCI bus,
31  * fix ATA Cable signal detection, fix incorrect /proc info
32  * add /proc display for per-drive PIO/DMA/UDMA mode and
33  * per-channel ATA-33/66 Cable detect.
34  *      Duncan Laurie <void@sun.com>
35  *
36  * fixup /proc output for multiple controllers
37  *      Tim Hockin <thockin@sun.com>
38  *
39  * On hpt366: 
40  * Reset the hpt366 on error, reset on dma
41  * Fix disabling Fast Interrupt hpt366.
42  *      Mike Waychison <crlf@sun.com>
43  */
44
45 #include <linux/config.h>
46 #include <linux/types.h>
47 #include <linux/kernel.h>
48 #include <linux/delay.h>
49 #include <linux/timer.h>
50 #include <linux/mm.h>
51 #include <linux/ioport.h>
52 #include <linux/blkdev.h>
53 #include <linux/hdreg.h>
54
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/init.h>
58 #include <linux/ide.h>
59
60 #include <asm/uaccess.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63
64 #include "ata-timing.h"
65
66 #define DISPLAY_HPT366_TIMINGS
67
68 /* various tuning parameters */
69 #define HPT_RESET_STATE_ENGINE
70 /*#define HPT_DELAY_INTERRUPT*/
71 /*#define HPT_SERIALIZE_IO*/
72
73 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
74 #include <linux/stat.h>
75 #include <linux/proc_fs.h>
76 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
77
78 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
79
80 const char *quirk_drives[] = {
81         "QUANTUM FIREBALLlct08 08",
82         "QUANTUM FIREBALLP KA6.4",
83         "QUANTUM FIREBALLP LM20.4",
84         "QUANTUM FIREBALLP LM20.5",
85         NULL
86 };
87
88 const char *bad_ata100_5[] = {
89         "IBM-DTLA-307075",
90         "IBM-DTLA-307060",
91         "IBM-DTLA-307045",
92         "IBM-DTLA-307030",
93         "IBM-DTLA-307020",
94         "IBM-DTLA-307015",
95         "IBM-DTLA-305040",
96         "IBM-DTLA-305030",
97         "IBM-DTLA-305020",
98         "IC35L010AVER07-0",
99         "IC35L020AVER07-0",
100         "IC35L030AVER07-0",
101         "IC35L040AVER07-0",
102         "IC35L060AVER07-0",
103         "WDC AC310200R",
104         NULL
105 };
106
107 const char *bad_ata66_4[] = {
108         "IBM-DTLA-307075",
109         "IBM-DTLA-307060",
110         "IBM-DTLA-307045",
111         "IBM-DTLA-307030",
112         "IBM-DTLA-307020",
113         "IBM-DTLA-307015",
114         "IBM-DTLA-305040",
115         "IBM-DTLA-305030",
116         "IBM-DTLA-305020",
117         "IC35L010AVER07-0",
118         "IC35L020AVER07-0",
119         "IC35L030AVER07-0",
120         "IC35L040AVER07-0",
121         "IC35L060AVER07-0",
122         "WDC AC310200R",
123         NULL
124 };
125
126 const char *bad_ata66_3[] = {
127         "WDC AC310200R",
128         NULL
129 };
130
131 const char *bad_ata33[] = {
132         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
133         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
134         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
135         "Maxtor 90510D4",
136         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
137         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
138         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
139         NULL
140 };
141
142 struct chipset_bus_clock_list_entry {
143         byte            xfer_speed;
144         unsigned int    chipset_settings;
145 };
146
147 /* key for bus clock timings
148  * bit
149  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
150  *        DMA. cycles = value + 1
151  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
152  *        DMA. cycles = value + 1
153  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
154  *        register access.
155  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
156  *        register access.
157  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
158  *        during task file register access.
159  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
160  *        xfer.
161  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
162  *        register access.
163  * 28     UDMA enable
164  * 29     DMA enable
165  * 30     PIO_MST enable. if set, the chip is in bus master mode during
166  *        PIO.
167  * 31     FIFO enable.
168  */
169 struct chipset_bus_clock_list_entry forty_base [] = {
170
171         {       XFER_UDMA_4,    0x900fd943      },
172         {       XFER_UDMA_3,    0x900ad943      },
173         {       XFER_UDMA_2,    0x900bd943      },
174         {       XFER_UDMA_1,    0x9008d943      },
175         {       XFER_UDMA_0,    0x9008d943      },
176
177         {       XFER_MW_DMA_2,  0xa008d943      },
178         {       XFER_MW_DMA_1,  0xa010d955      },
179         {       XFER_MW_DMA_0,  0xa010d9fc      },
180
181         {       XFER_PIO_4,     0xc008d963      },
182         {       XFER_PIO_3,     0xc010d974      },
183         {       XFER_PIO_2,     0xc010d997      },
184         {       XFER_PIO_1,     0xc010d9c7      },
185         {       XFER_PIO_0,     0xc018d9d9      },
186         {       0,              0x0120d9d9      }
187 };
188
189 struct chipset_bus_clock_list_entry thirty_three_base [] = {
190
191         {       XFER_UDMA_4,    0x90c9a731      },
192         {       XFER_UDMA_3,    0x90cfa731      },
193         {       XFER_UDMA_2,    0x90caa731      },
194         {       XFER_UDMA_1,    0x90cba731      },
195         {       XFER_UDMA_0,    0x90c8a731      },
196
197         {       XFER_MW_DMA_2,  0xa0c8a731      },
198         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
199         {       XFER_MW_DMA_0,  0xa0c8a797      },
200
201         {       XFER_PIO_4,     0xc0c8a731      },
202         {       XFER_PIO_3,     0xc0c8a742      },
203         {       XFER_PIO_2,     0xc0d0a753      },
204         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
205         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
206         {       0,              0x0120a7a7      }
207 };
208
209 struct chipset_bus_clock_list_entry twenty_five_base [] = {
210
211         {       XFER_UDMA_4,    0x90c98521      },
212         {       XFER_UDMA_3,    0x90cf8521      },
213         {       XFER_UDMA_2,    0x90cf8521      },
214         {       XFER_UDMA_1,    0x90cb8521      },
215         {       XFER_UDMA_0,    0x90cb8521      },
216
217         {       XFER_MW_DMA_2,  0xa0ca8521      },
218         {       XFER_MW_DMA_1,  0xa0ca8532      },
219         {       XFER_MW_DMA_0,  0xa0ca8575      },
220
221         {       XFER_PIO_4,     0xc0ca8521      },
222         {       XFER_PIO_3,     0xc0ca8532      },
223         {       XFER_PIO_2,     0xc0ca8542      },
224         {       XFER_PIO_1,     0xc0d08572      },
225         {       XFER_PIO_0,     0xc0d08585      },
226         {       0,              0x01208585      }
227 };
228
229 #if 1
230 /* these are the current (4 sep 2001) timings from highpoint */
231 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
232         {       XFER_UDMA_5,    0x12446231      },
233         {       XFER_UDMA_4,    0x12446231      },
234         {       XFER_UDMA_3,    0x126c6231      },
235         {       XFER_UDMA_2,    0x12486231      },
236         {       XFER_UDMA_1,    0x124c6233      },
237         {       XFER_UDMA_0,    0x12506297      },
238
239         {       XFER_MW_DMA_2,  0x22406c31      },
240         {       XFER_MW_DMA_1,  0x22406c33      },
241         {       XFER_MW_DMA_0,  0x22406c97      },
242
243         {       XFER_PIO_4,     0x06414e31      },
244         {       XFER_PIO_3,     0x06414e42      },
245         {       XFER_PIO_2,     0x06414e53      },
246         {       XFER_PIO_1,     0x06814e93      },
247         {       XFER_PIO_0,     0x06814ea7      },
248         {       0,              0x06814ea7      }
249 };
250
251 /* 2x 33MHz timings */
252 struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
253         {       XFER_UDMA_5,    0x1488e673       },
254         {       XFER_UDMA_4,    0x1488e673       },
255         {       XFER_UDMA_3,    0x1498e673       },
256         {       XFER_UDMA_2,    0x1490e673       },
257         {       XFER_UDMA_1,    0x1498e677       },
258         {       XFER_UDMA_0,    0x14a0e73f       },
259
260         {       XFER_MW_DMA_2,  0x2480fa73       },
261         {       XFER_MW_DMA_1,  0x2480fa77       }, 
262         {       XFER_MW_DMA_0,  0x2480fb3f       },
263
264         {       XFER_PIO_4,     0x0c82be73       },
265         {       XFER_PIO_3,     0x0c82be95       },
266         {       XFER_PIO_2,     0x0c82beb7       },
267         {       XFER_PIO_1,     0x0d02bf37       },
268         {       XFER_PIO_0,     0x0d02bf5f       },
269         {       0,              0x0d02bf5f       }
270 };
271 #else
272 /* from highpoint documentation. these are old values */
273 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
274         {       XFER_UDMA_5,    0x16454e31      },
275         {       XFER_UDMA_4,    0x16454e31      },
276         {       XFER_UDMA_3,    0x166d4e31      },
277         {       XFER_UDMA_2,    0x16494e31      },
278         {       XFER_UDMA_1,    0x164d4e31      },
279         {       XFER_UDMA_0,    0x16514e31      },
280
281         {       XFER_MW_DMA_2,  0x26514e21      },
282         {       XFER_MW_DMA_1,  0x26514e33      },
283         {       XFER_MW_DMA_0,  0x26514e97      },
284
285         {       XFER_PIO_4,     0x06514e21      },
286         {       XFER_PIO_3,     0x06514e22      },
287         {       XFER_PIO_2,     0x06514e33      },
288         {       XFER_PIO_1,     0x06914e43      },
289         {       XFER_PIO_0,     0x06914e57      },
290         {       0,              0x06514e57      }
291 };
292
293 struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
294         {       XFER_UDMA_5,    0x14846231      },
295         {       XFER_UDMA_4,    0x14886231      },
296         {       XFER_UDMA_3,    0x148c6231      },
297         {       XFER_UDMA_2,    0x148c6231      },
298         {       XFER_UDMA_1,    0x14906231      },
299         {       XFER_UDMA_0,    0x14986231      },
300         
301         {       XFER_MW_DMA_2,  0x26514e21      },
302         {       XFER_MW_DMA_1,  0x26514e33      },
303         {       XFER_MW_DMA_0,  0x26514e97      },
304         
305         {       XFER_PIO_4,     0x06514e21      },
306         {       XFER_PIO_3,     0x06514e22      },
307         {       XFER_PIO_2,     0x06514e33      },
308         {       XFER_PIO_1,     0x06914e43      },
309         {       XFER_PIO_0,     0x06914e57      },
310         {       0,              0x06514e57      }
311 };
312 #endif
313
314 struct chipset_bus_clock_list_entry fifty_base_hpt370[] = {
315         {       XFER_UDMA_5,    0x12848242      },
316         {       XFER_UDMA_4,    0x12ac8242      },
317         {       XFER_UDMA_3,    0x128c8242      },
318         {       XFER_UDMA_2,    0x120c8242      },
319         {       XFER_UDMA_1,    0x12148254      },
320         {       XFER_UDMA_0,    0x121882ea      },
321
322         {       XFER_MW_DMA_2,  0x22808242      },
323         {       XFER_MW_DMA_1,  0x22808254      },
324         {       XFER_MW_DMA_0,  0x228082ea      },
325
326         {       XFER_PIO_4,     0x0a81f442      },
327         {       XFER_PIO_3,     0x0a81f443      },
328         {       XFER_PIO_2,     0x0a81f454      },
329         {       XFER_PIO_1,     0x0ac1f465      },
330         {       XFER_PIO_0,     0x0ac1f48a      },
331         {       0,              0x0ac1f48a      }
332 };
333
334 #define HPT366_DEBUG_DRIVE_INFO         0
335 #define HPT370_ALLOW_ATA100_5           1
336 #define HPT366_ALLOW_ATA66_4            1
337 #define HPT366_ALLOW_ATA66_3            1
338 #define HPT366_MAX_DEVS                 8
339
340 #define F_LOW_PCI_33      0x23
341 #define F_LOW_PCI_40      0x29
342 #define F_LOW_PCI_50      0x2d
343 #define F_LOW_PCI_66      0x42
344
345 static struct pci_dev *hpt_devs[HPT366_MAX_DEVS];
346 static int n_hpt_devs;
347
348 static unsigned int pci_rev_check_hpt3xx(struct pci_dev *dev);
349 static unsigned int pci_rev2_check_hpt3xx(struct pci_dev *dev);
350 byte hpt366_proc = 0;
351 byte hpt363_shared_irq;
352 byte hpt363_shared_pin;
353 extern char *ide_xfer_verbose (byte xfer_rate);
354
355 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
356 static int hpt366_get_info(char *, char **, off_t, int);
357 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
358
359 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
360 {
361         char *p = buffer;
362         char *chipset_nums[] = {"366", "366", "368", "370", "370A"};
363         int i;
364
365         p += sprintf(p, "\n                             "
366                 "HighPoint HPT366/368/370\n");
367         for (i = 0; i < n_hpt_devs; i++) {
368                 struct pci_dev *dev = hpt_devs[i];
369                 unsigned short iobase = dev->resource[4].start;
370                 u32 class_rev;
371                 u8 c0, c1;
372
373                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
374                 class_rev &= 0xff;
375
376                 p += sprintf(p, "\nController: %d\n", i);
377                 p += sprintf(p, "Chipset: HPT%s\n",
378                         class_rev < sizeof(chipset_nums) / sizeof(char *) ? chipset_nums[class_rev] : "???");
379                 p += sprintf(p, "--------------- Primary Channel "
380                                 "--------------- Secondary Channel "
381                                 "--------------\n");
382
383                 /* get the bus master status registers */
384                 c0 = inb_p(iobase + 0x2);
385                 c1 = inb_p(iobase + 0xa);
386                 p += sprintf(p, "Enabled:        %s"
387                                 "                             %s\n",
388                         (c0 & 0x80) ? "no" : "yes",
389                         (c1 & 0x80) ? "no" : "yes");
390
391                 if (pci_rev_check_hpt3xx(dev)) {
392                         u8 cbl;
393                         cbl = inb_p(iobase + 0x7b);
394                         outb_p(cbl | 1, iobase + 0x7b);
395                         outb_p(cbl & ~1, iobase + 0x7b);
396                         cbl = inb_p(iobase + 0x7a);
397                         p += sprintf(p, "Cable:          ATA-%d"
398                                         "                          ATA-%d\n",
399                                 (cbl & 0x02) ? 33 : 66,
400                                 (cbl & 0x01) ? 33 : 66);
401                         p += sprintf(p, "\n");
402                 }
403
404                 p += sprintf(p, "--------------- drive0 --------- drive1 "
405                                 "------- drive0 ---------- drive1 -------\n");
406                 p += sprintf(p, "DMA capable:    %s              %s" 
407                                 "            %s               %s\n",
408                         (c0 & 0x20) ? "yes" : "no ", 
409                         (c0 & 0x40) ? "yes" : "no ",
410                         (c1 & 0x20) ? "yes" : "no ", 
411                         (c1 & 0x40) ? "yes" : "no ");
412
413                 {
414                         u8 c2, c3;
415                         /* older revs don't have these registers mapped 
416                          * into io space */
417                         pci_read_config_byte(dev, 0x43, &c0);
418                         pci_read_config_byte(dev, 0x47, &c1);
419                         pci_read_config_byte(dev, 0x4b, &c2);
420                         pci_read_config_byte(dev, 0x4f, &c3);
421
422                         p += sprintf(p, "Mode:           %s             %s"
423                                         "           %s              %s\n",
424                                 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " : 
425                                         (c0 & 0x80) ? "PIO " : "off ",
426                                 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
427                                         (c1 & 0x80) ? "PIO " : "off ",
428                                 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
429                                         (c2 & 0x80) ? "PIO " : "off ",
430                                 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
431                                         (c3 & 0x80) ? "PIO " : "off ");
432                 }
433         }
434         p += sprintf(p, "\n");
435         
436         return p-buffer;/* => must be less than 4k! */
437 }
438 #endif  /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
439
440 static unsigned int pci_rev_check_hpt3xx (struct pci_dev *dev)
441 {
442         unsigned int class_rev;
443         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
444         class_rev &= 0xff;
445         return ((int) (class_rev > 0x02) ? 1 : 0);
446 }
447
448 static unsigned int pci_rev2_check_hpt3xx (struct pci_dev *dev)
449 {
450         unsigned int class_rev;
451         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
452         class_rev &= 0xff;
453         return ((int) (class_rev > 0x01) ? 1 : 0);
454 }
455
456 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
457 {
458         struct hd_driveid *id = drive->id;
459
460         if (quirk_drives == list) {
461                 while (*list) {
462                         if (strstr(id->model, *list++)) {
463                                 return 1;
464                         }
465                 }
466         } else {
467                 while (*list) {
468                         if (!strcmp(*list++,id->model)) {
469                                 return 1;
470                         }
471                 }
472         }
473         return 0;
474 }
475
476 static unsigned int pci_bus_clock_list (byte speed, struct chipset_bus_clock_list_entry * chipset_table)
477 {
478         for ( ; chipset_table->xfer_speed ; chipset_table++)
479                 if (chipset_table->xfer_speed == speed) {
480                         return chipset_table->chipset_settings;
481                 }
482         return chipset_table->chipset_settings;
483 }
484
485 static void hpt366_tune_chipset (ide_drive_t *drive, byte speed)
486 {
487         byte regtime            = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
488         byte regfast            = (drive->channel->unit) ? 0x55 : 0x51;
489                         /*
490                          * since the channel is always 0 it does not matter.
491                          */
492
493         unsigned int reg1       = 0;
494         unsigned int reg2       = 0;
495         byte drive_fast         = 0;
496
497         /*
498          * Disable the "fast interrupt" prediction. 
499          */
500         pci_read_config_byte(drive->channel->pci_dev, regfast, &drive_fast);
501         if (drive_fast & 0x02)
502                 pci_write_config_byte(drive->channel->pci_dev, regfast, drive_fast & ~0x20);
503
504         pci_read_config_dword(drive->channel->pci_dev, regtime, &reg1);
505         /* detect bus speed by looking at control reg timing: */
506         switch((reg1 >> 8) & 7) {
507                 case 5:
508                         reg2 = pci_bus_clock_list(speed, forty_base);
509                         break;
510                 case 9:
511                         reg2 = pci_bus_clock_list(speed, twenty_five_base);
512                         break;
513                 default:
514                 case 7:
515                         reg2 = pci_bus_clock_list(speed, thirty_three_base);
516                         break;
517         }
518 #if 0
519         /* this is a nice idea ... */
520         list_conf = pci_bus_clock_list(speed,
521                                        (struct chipset_bus_clock_list_entry *)
522                                        dev->sysdata);
523 #endif
524         /*
525          * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
526          */
527         if (speed >= XFER_MW_DMA_0) {
528                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
529         } else {
530                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
531         }       
532         reg2 &= ~0x80000000;
533
534         pci_write_config_dword(drive->channel->pci_dev, regtime, reg2);
535 }
536
537 static void hpt370_tune_chipset (ide_drive_t *drive, byte speed)
538 {
539         byte regfast            = (drive->channel->unit) ? 0x55 : 0x51;
540         unsigned int list_conf  = 0;
541         unsigned int drive_conf = 0;
542         unsigned int conf_mask  = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
543         byte drive_pci          = 0x40 + (drive->dn * 4);
544         byte new_fast, drive_fast               = 0;
545         struct pci_dev *dev     = drive->channel->pci_dev;
546
547         /*
548          * Disable the "fast interrupt" prediction.
549          * don't holdoff on interrupts. (== 0x01 despite what the docs say) 
550          */
551         pci_read_config_byte(dev, regfast, &drive_fast);
552         new_fast = drive_fast;
553         if (new_fast & 0x02)
554                 new_fast &= ~0x02;
555
556 #ifdef HPT_DELAY_INTERRUPT
557         if (new_fast & 0x01)
558                 new_fast &= ~0x01;
559 #else
560         if ((new_fast & 0x01) == 0)
561                 new_fast |= 0x01;
562 #endif
563         if (new_fast != drive_fast)
564                 pci_write_config_byte(drive->channel->pci_dev, regfast, new_fast);
565
566         list_conf = pci_bus_clock_list(speed, 
567                                        (struct chipset_bus_clock_list_entry *)
568                                        dev->sysdata);
569
570         pci_read_config_dword(dev, drive_pci, &drive_conf);
571         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
572         
573         if (speed < XFER_MW_DMA_0) {
574                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
575         }
576
577         pci_write_config_dword(dev, drive_pci, list_conf);
578 }
579
580 static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed)
581 {
582         if ((drive->type != ATA_DISK) && (speed < XFER_SW_DMA_0))
583                 return -1;
584
585         if (!drive->init_speed)
586                 drive->init_speed = speed;
587
588         if (pci_rev_check_hpt3xx(drive->channel->pci_dev)) {
589                 hpt370_tune_chipset(drive, speed);
590         } else {
591                 hpt366_tune_chipset(drive, speed);
592         }
593         drive->current_speed = speed;
594         return ((int) ide_config_drive_speed(drive, speed));
595 }
596
597 static void config_chipset_for_pio (ide_drive_t *drive)
598 {
599         unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
600         unsigned short xfer_pio = drive->id->eide_pio_modes;
601         byte    timing, speed, pio;
602
603         pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
604
605         if (xfer_pio > 4)
606                 xfer_pio = 0;
607
608         if (drive->id->eide_pio_iordy > 0) {
609                 for (xfer_pio = 5;
610                         xfer_pio>0 &&
611                         drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
612                         xfer_pio--);
613         } else {
614                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
615                            (drive->id->eide_pio_modes & 2) ? 0x04 :
616                            (drive->id->eide_pio_modes & 1) ? 0x03 :
617                            (drive->id->tPIO & 2) ? 0x02 :
618                            (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
619         }
620
621         timing = (xfer_pio >= pio) ? xfer_pio : pio;
622
623         switch(timing) {
624                 case 4: speed = XFER_PIO_4;break;
625                 case 3: speed = XFER_PIO_3;break;
626                 case 2: speed = XFER_PIO_2;break;
627                 case 1: speed = XFER_PIO_1;break;
628                 default:
629                         speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
630                         break;
631         }
632         (void) hpt3xx_tune_chipset(drive, speed);
633 }
634
635 static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio)
636 {
637         byte speed;
638         switch(pio) {
639                 case 4:         speed = XFER_PIO_4;break;
640                 case 3:         speed = XFER_PIO_3;break;
641                 case 2:         speed = XFER_PIO_2;break;
642                 case 1:         speed = XFER_PIO_1;break;
643                 default:        speed = XFER_PIO_0;break;
644         }
645         (void) hpt3xx_tune_chipset(drive, speed);
646 }
647
648 #ifdef CONFIG_BLK_DEV_IDEDMA
649 /*
650  * This allows the configuration of ide_pci chipset registers
651  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
652  * after the drive is reported by the OS.  Initally for designed for
653  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
654  *
655  * check_in_drive_lists(drive, bad_ata66_4)
656  * check_in_drive_lists(drive, bad_ata66_3)
657  * check_in_drive_lists(drive, bad_ata33)
658  *
659  */
660 static int config_chipset_for_dma (ide_drive_t *drive)
661 {
662         struct hd_driveid *id   = drive->id;
663         byte speed              = 0x00;
664         byte ultra66            = eighty_ninty_three(drive);
665         int  rval;
666
667         if ((drive->type != ATA_DISK) && (speed < XFER_SW_DMA_0))
668                 return ((int) ide_dma_off_quietly);
669
670         if ((id->dma_ultra & 0x0020) &&
671             (!check_in_drive_lists(drive, bad_ata100_5)) &&
672             (HPT370_ALLOW_ATA100_5) &&
673             (pci_rev_check_hpt3xx(drive->channel->pci_dev)) &&
674             (ultra66)) {
675                 speed = XFER_UDMA_5;
676         } else if ((id->dma_ultra & 0x0010) &&
677                    (!check_in_drive_lists(drive, bad_ata66_4)) &&
678                    (HPT366_ALLOW_ATA66_4) &&
679                    (ultra66)) {
680                 speed = XFER_UDMA_4;
681         } else if ((id->dma_ultra & 0x0008) &&
682                    (!check_in_drive_lists(drive, bad_ata66_3)) &&
683                    (HPT366_ALLOW_ATA66_3) &&
684                    (ultra66)) {
685                 speed = XFER_UDMA_3;
686         } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) {
687                 if (id->dma_ultra & 0x0004) {
688                         speed = XFER_UDMA_2;
689                 } else if (id->dma_ultra & 0x0002) {
690                         speed = XFER_UDMA_1;
691                 } else if (id->dma_ultra & 0x0001) {
692                         speed = XFER_UDMA_0;
693                 }
694         } else if (id->dma_mword & 0x0004) {
695                 speed = XFER_MW_DMA_2;
696         } else if (id->dma_mword & 0x0002) {
697                 speed = XFER_MW_DMA_1;
698         } else if (id->dma_mword & 0x0001) {
699                 speed = XFER_MW_DMA_0;
700         } else {
701                 return ((int) ide_dma_off_quietly);
702         }
703
704         (void) hpt3xx_tune_chipset(drive, speed);
705
706         rval = (int)(   ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
707                         ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
708                         ((id->dma_mword >> 8) & 7) ? ide_dma_on :
709                                                      ide_dma_off_quietly);
710         return rval;
711 }
712
713 int hpt3xx_quirkproc (ide_drive_t *drive)
714 {
715         return ((int) check_in_drive_lists(drive, quirk_drives));
716 }
717
718 void hpt3xx_intrproc (ide_drive_t *drive)
719 {
720         if (drive->quirk_list) {
721                 /* drives in the quirk_list may not like intr setups/cleanups */
722         } else {
723                 OUT_BYTE((drive)->ctl|2, drive->channel->io_ports[IDE_CONTROL_OFFSET]);
724         }
725 }
726
727 void hpt3xx_maskproc (ide_drive_t *drive, int mask)
728 {
729         if (drive->quirk_list) {
730                 if (pci_rev_check_hpt3xx(drive->channel->pci_dev)) {
731                         byte reg5a = 0;
732                         pci_read_config_byte(drive->channel->pci_dev, 0x5a, &reg5a);
733                         if (((reg5a & 0x10) >> 4) != mask)
734                                 pci_write_config_byte(drive->channel->pci_dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
735                 } else {
736                         if (mask) {
737                                 disable_irq(drive->channel->irq);
738                         } else {
739                                 enable_irq(drive->channel->irq);
740                         }
741                 }
742         } else {
743                 if (IDE_CONTROL_REG)
744                         OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG);
745         }
746 }
747
748 static int config_drive_xfer_rate (ide_drive_t *drive)
749 {
750         struct hd_driveid *id = drive->id;
751         ide_dma_action_t dma_func = ide_dma_on;
752
753         if (id && (id->capability & 1) && drive->channel->autodma) {
754                 /* Consult the list of known "bad" drives */
755                 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
756                         dma_func = ide_dma_off;
757                         goto fast_ata_pio;
758                 }
759                 dma_func = ide_dma_off_quietly;
760                 if (id->field_valid & 4) {
761                         if (id->dma_ultra & 0x002F) {
762                                 /* Force if Capable UltraDMA */
763                                 dma_func = config_chipset_for_dma(drive);
764                                 if ((id->field_valid & 2) &&
765                                     (dma_func != ide_dma_on))
766                                         goto try_dma_modes;
767                         }
768                 } else if (id->field_valid & 2) {
769 try_dma_modes:
770                         if (id->dma_mword & 0x0007) {
771                                 /* Force if Capable regular DMA modes */
772                                 dma_func = config_chipset_for_dma(drive);
773                                 if (dma_func != ide_dma_on)
774                                         goto no_dma_set;
775                         }
776                 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
777                         if (id->eide_dma_time > 150) {
778                                 goto no_dma_set;
779                         }
780                         /* Consult the list of known "good" drives */
781                         dma_func = config_chipset_for_dma(drive);
782                         if (dma_func != ide_dma_on)
783                                 goto no_dma_set;
784                 } else {
785                         goto fast_ata_pio;
786                 }
787         } else if ((id->capability & 8) || (id->field_valid & 2)) {
788 fast_ata_pio:
789                 dma_func = ide_dma_off_quietly;
790 no_dma_set:
791
792                 config_chipset_for_pio(drive);
793         }
794         return drive->channel->dmaproc(dma_func, drive);
795 }
796
797 /*
798  * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
799  *
800  * This is specific to the HPT366 UDMA bios chipset
801  * by HighPoint|Triones Technologies, Inc.
802  */
803 int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
804 {
805         byte reg50h = 0, reg52h = 0, reg5ah = 0, dma_stat = 0;
806         unsigned long dma_base = drive->channel->dma_base;
807
808         switch (func) {
809                 case ide_dma_check:
810                         return config_drive_xfer_rate(drive);
811                 case ide_dma_test_irq:  /* returns 1 if dma irq issued, 0 otherwise */
812                         dma_stat = inb(dma_base+2);
813                         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
814                 case ide_dma_lostirq:
815                         pci_read_config_byte(drive->channel->pci_dev, 0x50, &reg50h);
816                         pci_read_config_byte(drive->channel->pci_dev, 0x52, &reg52h);
817                         pci_read_config_byte(drive->channel->pci_dev, 0x5a, &reg5ah);
818                         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
819                                 drive->name,
820                                 ide_dmafunc_verbose(func),
821                                 reg50h, reg52h, reg5ah);
822                         if (reg5ah & 0x10)
823                                 pci_write_config_byte(drive->channel->pci_dev, 0x5a, reg5ah & ~0x10);
824                         /* fall through to a reset */
825 #if 0
826                 case ide_dma_begin:
827                 case ide_dma_end:
828                         /* reset the chips state over and over.. */
829                         pci_write_config_byte(drive->channel->pci_dev, 0x51, 0x13);
830 #endif
831                         break;
832                 case ide_dma_timeout:
833                 default:
834                         break;
835         }
836         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
837 }
838
839 int hpt370_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
840 {
841         struct ata_channel *hwif = drive->channel;
842         unsigned long dma_base = hwif->dma_base;
843         byte regstate = hwif->unit ? 0x54 : 0x50;
844         byte reginfo = hwif->unit ? 0x56 : 0x52;
845         byte dma_stat;
846
847         switch (func) {
848                 case ide_dma_check:
849                         return config_drive_xfer_rate(drive);
850                 case ide_dma_test_irq:  /* returns 1 if dma irq issued, 0 otherwise */
851                         dma_stat = inb(dma_base+2);
852                         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
853
854                 case ide_dma_end:
855                         dma_stat = inb(dma_base + 2);
856                         if (dma_stat & 0x01) {
857                                 udelay(20); /* wait a little */
858                                 dma_stat = inb(dma_base + 2);
859                         }
860                         if ((dma_stat & 0x01) == 0) 
861                                 break;
862
863                         func = ide_dma_timeout;
864                         /* fallthrough */
865
866                 case ide_dma_timeout:
867                 case ide_dma_lostirq:
868                         pci_read_config_byte(hwif->pci_dev, reginfo, 
869                                              &dma_stat); 
870                         printk("%s: %d bytes in FIFO\n", drive->name, 
871                                dma_stat);
872                         pci_write_config_byte(hwif->pci_dev, regstate, 0x37);
873                         udelay(10);
874                         dma_stat = inb(dma_base);
875                         outb(dma_stat & ~0x1, dma_base); /* stop dma */
876                         dma_stat = inb(dma_base + 2); 
877                         outb(dma_stat | 0x6, dma_base+2); /* clear errors */
878                         /* fallthrough */
879
880 #ifdef HPT_RESET_STATE_ENGINE
881                 case ide_dma_begin:
882 #endif
883                         pci_write_config_byte(hwif->pci_dev, regstate, 0x37);
884                         udelay(10);
885                         break;
886
887                 default:
888                         break;
889         }
890         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
891 }
892 #endif /* CONFIG_BLK_DEV_IDEDMA */
893
894 /*
895  * Since SUN Cobalt is attempting to do this operation, I should disclose
896  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
897  * HOTSWAP ATA Infrastructure.
898  */
899 void hpt3xx_reset (ide_drive_t *drive)
900 {
901 #if 0
902         unsigned long high_16   = pci_resource_start(drive->channel->pci_dev, 4);
903         byte reset              = (drive->channel->unit) ? 0x80 : 0x40;
904         byte reg59h             = 0;
905
906         pci_read_config_byte(drive->channel->pci_dev, 0x59, &reg59h);
907         pci_write_config_byte(drive->channel->pci_dev, 0x59, reg59h|reset);
908         pci_write_config_byte(drive->channel->pci_dev, 0x59, reg59h);
909 #endif
910 }
911
912 #if 0
913 static int hpt3xx_tristate (ide_drive_t * drive, int state)
914 {
915         struct ata_channel *hwif        = drive->channel;
916         struct pci_dev *dev     = hwif->pci_dev;
917         byte reset              = (hwif->unit) ? 0x80 : 0x40;
918         byte state_reg          = (hwif->unit) ? 0x57 : 0x53;
919         byte reg59h             = 0;
920         byte regXXh             = 0;
921
922         if (!hwif)
923                 return -EINVAL;
924
925 //      hwif->bus_state = state;
926
927         pci_read_config_byte(dev, 0x59, &reg59h);
928         pci_read_config_byte(dev, state_reg, &regXXh);
929
930         if (state) {
931                 // reset drives...
932                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
933                 pci_write_config_byte(dev, 0x59, reg59h|reset);
934         } else {
935                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
936                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
937                 // reset drives...
938         }
939         return 0;
940 }
941 #endif
942
943 /* 
944  * set/get power state for a drive.
945  * turning the power off does the following things:
946  *   1) soft-reset the drive
947  *   2) tri-states the ide bus
948  *
949  * when we turn things back on, we need to re-initialize things.
950  */
951 #define TRISTATE_BIT  0x8000
952 static int hpt370_busproc(ide_drive_t * drive, int state)
953 {
954         struct ata_channel *hwif = drive->channel;
955         byte tristate, resetmask, bus_reg;
956         u16 tri_reg;
957
958         if (!hwif)
959                 return -EINVAL;
960
961         hwif->bus_state = state;
962
963         if (hwif->unit) { 
964                 /* secondary channel */
965                 tristate = 0x56;
966                 resetmask = 0x80; 
967         } else { 
968                 /* primary channel */
969                 tristate = 0x52;
970                 resetmask = 0x40;
971         }
972
973         /* grab status */
974         pci_read_config_word(hwif->pci_dev, tristate, &tri_reg);
975         pci_read_config_byte(hwif->pci_dev, 0x59, &bus_reg);
976
977         /* set the state. we don't set it if we don't need to do so.
978          * make sure that the drive knows that it has failed if it's off */
979         switch (state) {
980         case BUSSTATE_ON:
981                 hwif->drives[0].failures = 0;
982                 hwif->drives[1].failures = 0;
983                 if ((bus_reg & resetmask) == 0)
984                         return 0;
985                 tri_reg &= ~TRISTATE_BIT;
986                 bus_reg &= ~resetmask;
987                 break;
988         case BUSSTATE_OFF:
989                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
990                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
991                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
992                         return 0;
993                 tri_reg &= ~TRISTATE_BIT;
994                 bus_reg |= resetmask;
995                 break;
996         case BUSSTATE_TRISTATE:
997                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
998                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
999                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1000                         return 0;
1001                 tri_reg |= TRISTATE_BIT;
1002                 bus_reg |= resetmask;
1003                 break;
1004         }
1005         pci_write_config_byte(hwif->pci_dev, 0x59, bus_reg);
1006         pci_write_config_word(hwif->pci_dev, tristate, tri_reg);
1007
1008         return 0;
1009 }
1010
1011 static void __init init_hpt370(struct pci_dev *dev)
1012 {
1013         int adjust, i;
1014         u16 freq;
1015         u32 pll;
1016         byte reg5bh;
1017
1018         /*
1019          * default to pci clock. make sure MA15/16 are set to output
1020          * to prevent drives having problems with 40-pin cables.
1021          */
1022         pci_write_config_byte(dev, 0x5b, 0x23);
1023
1024         /*
1025          * set up the PLL. we need to adjust it so that it's stable. 
1026          * freq = Tpll * 192 / Tpci
1027          */
1028         pci_read_config_word(dev, 0x78, &freq);
1029         freq &= 0x1FF;
1030         if (freq < 0x9c) {
1031                 pll = F_LOW_PCI_33;
1032                 dev->sysdata = (void *) thirty_three_base_hpt370;
1033                 printk("HPT370: using 33MHz PCI clock\n");
1034         } else if (freq < 0xb0) {
1035                 pll = F_LOW_PCI_40;
1036         } else if (freq < 0xc8) {
1037                 pll = F_LOW_PCI_50;
1038                 dev->sysdata = (void *) fifty_base_hpt370;
1039                 printk("HPT370: using 50MHz PCI clock\n");
1040         } else {
1041                 pll = F_LOW_PCI_66;
1042                 dev->sysdata = (void *) sixty_six_base_hpt370;
1043                 printk("HPT370: using 66MHz PCI clock\n");
1044         }
1045         
1046         /*
1047          * only try the pll if we don't have a table for the clock
1048          * speed that we're running at. NOTE: the internal PLL will
1049          * result in slow reads when using a 33MHz PCI clock. we also
1050          * don't like to use the PLL because it will cause glitches
1051          * on PRST/SRST when the HPT state engine gets reset.
1052          */
1053         if (dev->sysdata) 
1054                 goto init_hpt370_done;
1055         
1056         /*
1057          * adjust PLL based upon PCI clock, enable it, and wait for
1058          * stabilization.
1059          */
1060         adjust = 0;
1061         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1062         while (adjust++ < 6) {
1063                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1064                                        pll | 0x100);
1065
1066                 /* wait for clock stabilization */
1067                 for (i = 0; i < 0x50000; i++) {
1068                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1069                         if (reg5bh & 0x80) {
1070                                 /* spin looking for the clock to destabilize */
1071                                 for (i = 0; i < 0x1000; ++i) {
1072                                         pci_read_config_byte(dev, 0x5b, 
1073                                                              &reg5bh);
1074                                         if ((reg5bh & 0x80) == 0)
1075                                                 goto pll_recal;
1076                                 }
1077                                 pci_read_config_dword(dev, 0x5c, &pll);
1078                                 pci_write_config_dword(dev, 0x5c, 
1079                                                        pll & ~0x100);
1080                                 pci_write_config_byte(dev, 0x5b, 0x21);
1081                                 dev->sysdata = (void *) fifty_base_hpt370;
1082                                 printk("HPT370: using 50MHz internal PLL\n");
1083                                 goto init_hpt370_done;
1084                         }
1085                 }
1086 pll_recal:
1087                 if (adjust & 1)
1088                         pll -= (adjust >> 1);
1089                 else
1090                         pll += (adjust >> 1);
1091         } 
1092
1093 init_hpt370_done:
1094         /* reset state engine */
1095         pci_write_config_byte(dev, 0x50, 0x37); 
1096         pci_write_config_byte(dev, 0x54, 0x37); 
1097         udelay(100);
1098 }
1099
1100 unsigned int __init pci_init_hpt366(struct pci_dev *dev)
1101 {
1102         byte test = 0;
1103
1104         if (dev->resource[PCI_ROM_RESOURCE].start)
1105                 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1106
1107         pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1108         if (test != (L1_CACHE_BYTES / 4))
1109                 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1110
1111         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1112         if (test != 0x78)
1113                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1114
1115         pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1116         if (test != 0x08)
1117                 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1118
1119         pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1120         if (test != 0x08)
1121                 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1122
1123         if (pci_rev_check_hpt3xx(dev))
1124                 init_hpt370(dev);
1125
1126         if (n_hpt_devs < HPT366_MAX_DEVS)
1127                 hpt_devs[n_hpt_devs++] = dev;
1128         
1129 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
1130         if (!hpt366_proc) {
1131                 hpt366_proc = 1;
1132                 hpt366_display_info = &hpt366_get_info;
1133         }
1134 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
1135
1136         return dev->irq;
1137 }
1138
1139 unsigned int __init ata66_hpt366(struct ata_channel *hwif)
1140 {
1141         byte ata66      = 0;
1142         byte regmask    = (hwif->unit) ? 0x01 : 0x02;
1143
1144         pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
1145 #ifdef DEBUG
1146         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1147                 ata66, (ata66 & regmask) ? "33" : "66",
1148                 PCI_FUNC(hwif->pci_dev->devfn));
1149 #endif /* DEBUG */
1150         return ((ata66 & regmask) ? 0 : 1);
1151 }
1152
1153 void __init ide_init_hpt366(struct ata_channel *hwif)
1154 {
1155         int hpt_rev;
1156
1157         hwif->tuneproc  = &hpt3xx_tune_drive;
1158         hwif->speedproc = &hpt3xx_tune_chipset;
1159         hwif->quirkproc = &hpt3xx_quirkproc;
1160         hwif->intrproc  = &hpt3xx_intrproc;
1161         hwif->maskproc  = &hpt3xx_maskproc;
1162
1163 #ifdef HPT_SERIALIZE_IO
1164         /* serialize access to this device */
1165         if (hwif->mate)
1166                 hwif->serialized = hwif->mate->serialized = 1;
1167 #endif
1168
1169         hpt_rev = pci_rev_check_hpt3xx(hwif->pci_dev);
1170         if (hpt_rev) {
1171                 /* set up ioctl for power status. note: power affects both
1172                  * drives on each channel */
1173                 hwif->busproc   = &hpt370_busproc;
1174         }
1175
1176         if (pci_rev2_check_hpt3xx(hwif->pci_dev)) {
1177                 /* do nothing now but will split device types */
1178                 hwif->resetproc = &hpt3xx_reset;
1179 /*
1180  * don't do until we can parse out the cobalt box argh ...
1181  *              hwif->busproc   = &hpt3xx_tristate;
1182  */
1183         }
1184
1185 #ifdef CONFIG_BLK_DEV_IDEDMA
1186         if (hwif->dma_base) {
1187                 if (hpt_rev) {
1188                         byte reg5ah = 0;
1189                         pci_read_config_byte(hwif->pci_dev, 0x5a, &reg5ah);
1190                         if (reg5ah & 0x10)      /* interrupt force enable */
1191                                 pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10);
1192                         hwif->dmaproc = &hpt370_dmaproc;
1193                 } else {
1194                         hwif->dmaproc = &hpt366_dmaproc;
1195                 }
1196                 if (!noautodma)
1197                         hwif->autodma = 1;
1198                 else
1199                         hwif->autodma = 0;
1200                 hwif->highmem = 1;
1201         } else {
1202                 hwif->autodma = 0;
1203                 hwif->drives[0].autotune = 1;
1204                 hwif->drives[1].autotune = 1;
1205         }
1206 #else /* !CONFIG_BLK_DEV_IDEDMA */
1207         hwif->drives[0].autotune = 1;
1208         hwif->drives[1].autotune = 1;
1209         hwif->autodma = 0;
1210 #endif /* CONFIG_BLK_DEV_IDEDMA */
1211 }
1212
1213 void __init ide_dmacapable_hpt366(struct ata_channel *hwif, unsigned long dmabase)
1214 {
1215         byte masterdma = 0, slavedma = 0;
1216         byte dma_new = 0, dma_old = inb(dmabase+2);
1217         byte primary    = hwif->unit ? 0x4b : 0x43;
1218         byte secondary  = hwif->unit ? 0x4f : 0x47;
1219         unsigned long flags;
1220
1221         __save_flags(flags);    /* local CPU only */
1222         __cli();                /* local CPU only */
1223
1224         dma_new = dma_old;
1225         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1226         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1227
1228         if (masterdma & 0x30)   dma_new |= 0x20;
1229         if (slavedma & 0x30)    dma_new |= 0x40;
1230         if (dma_new != dma_old) outb(dma_new, dmabase+2);
1231
1232         __restore_flags(flags); /* local CPU only */
1233
1234         ide_setup_dma(hwif, dmabase, 8);
1235 }