[PATCH] 2.5.7 IDE 27
[opensuse:kernel.git] / drivers / ide / pdc202xx.c
1 /*
2  *  linux/drivers/ide/pdc202xx.c        Version 0.30    Mar. 18, 2000
3  *
4  *  Copyright (C) 1998-2000     Andre Hedrick <andre@linux-ide.org>
5  *  May be copied or modified under the terms of the GNU General Public License
6  *
7  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8  *  compiled into the kernel if you have more than one card installed.
9  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
10  *  safe chipset tuning, including this support is harmless
11  *
12  *  Promise Ultra66 cards with BIOS v1.11 this
13  *  compiled into the kernel if you have more than one card installed.
14  *
15  *  Promise Ultra100 cards.
16  *
17  *  The latest chipset code will support the following ::
18  *  Three Ultra33 controllers and 12 drives.
19  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
20  *  The 8/4 ratio is a BIOS code limit by promise.
21  *
22  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
23  *
24  */
25
26 /*
27  *  Portions Copyright (C) 1999 Promise Technology, Inc.
28  *  Author: Frank Tiernan (frankt@promise.com)
29  *  Released under terms of General Public License
30  */
31
32 #include <linux/config.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
37 #include <linux/mm.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48
49 #include "ata-timing.h"
50
51 #define PDC202XX_DEBUG_DRIVE_INFO               0
52 #define PDC202XX_DECODE_REGISTER_INFO           0
53
54 #define DISPLAY_PDC202XX_TIMINGS
55
56 #ifndef SPLIT_BYTE
57 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
58 #endif
59
60 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
61 #include <linux/stat.h>
62 #include <linux/proc_fs.h>
63
64 static int pdc202xx_get_info(char *, char **, off_t, int);
65 extern int (*pdc202xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
66 static struct pci_dev *bmide_dev;
67
68 char *pdc202xx_pio_verbose (u32 drive_pci)
69 {
70         if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
71         if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
72         if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
73         if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
74         if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
75         if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
76         return("PIO ?");
77 }
78
79 char *pdc202xx_dma_verbose (u32 drive_pci)
80 {
81         if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
82         if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
83         if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
84         if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
85         if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
86         if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
87         return("PIO---");
88 }
89
90 char *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
91 {
92         if ((drive_pci & 0x000ff000) == 0x000ff000)
93                 return("NOTSET");
94         if ((drive_pci & 0x00012000) == 0x00012000)
95                 return((slow_cable) ? "UDMA 2" : "UDMA 4");
96         if ((drive_pci & 0x00024000) == 0x00024000)
97                 return((slow_cable) ? "UDMA 1" : "UDMA 3");
98         if ((drive_pci & 0x00036000) == 0x00036000)
99                 return("UDMA 0");
100         return(pdc202xx_dma_verbose(drive_pci));
101 }
102
103 static char * pdc202xx_info (char *buf, struct pci_dev *dev)
104 {
105         char *p = buf;
106
107         u32 bibma  = pci_resource_start(dev, 4);
108         u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
109         u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
110         u8 hi = 0, lo = 0;
111
112         /*
113          * at that point bibma+0x2 et bibma+0xa are byte registers
114          * to investigate:
115          */
116         u8 c0   = inb_p((unsigned short)bibma + 0x02);
117         u8 c1   = inb_p((unsigned short)bibma + 0x0a);
118
119         u8 sc11 = inb_p((unsigned short)bibma + 0x11);
120         u8 sc1a = inb_p((unsigned short)bibma + 0x1a);
121         u8 sc1b = inb_p((unsigned short)bibma + 0x1b);
122         u8 sc1c = inb_p((unsigned short)bibma + 0x1c); 
123         u8 sc1d = inb_p((unsigned short)bibma + 0x1d);
124         u8 sc1e = inb_p((unsigned short)bibma + 0x1e);
125         u8 sc1f = inb_p((unsigned short)bibma + 0x1f);
126
127         pci_read_config_word(dev, 0x50, &reg50h);
128         pci_read_config_dword(dev, 0x60, &reg60h);
129         pci_read_config_dword(dev, 0x64, &reg64h);
130         pci_read_config_dword(dev, 0x68, &reg68h);
131         pci_read_config_dword(dev, 0x6c, &reg6ch);
132
133         switch(dev->device) {
134                 case PCI_DEVICE_ID_PROMISE_20267:
135                         p += sprintf(p, "\n                                PDC20267 Chipset.\n");
136                         break;
137                 case PCI_DEVICE_ID_PROMISE_20265:
138                         p += sprintf(p, "\n                                PDC20265 Chipset.\n");
139                         break;
140                 case PCI_DEVICE_ID_PROMISE_20262:
141                         p += sprintf(p, "\n                                PDC20262 Chipset.\n");
142                         break;
143                 case PCI_DEVICE_ID_PROMISE_20246:
144                         p += sprintf(p, "\n                                PDC20246 Chipset.\n");
145                         reg50h |= 0x0c00;
146                         break;
147                 default:
148                         p += sprintf(p, "\n                                PDC202XX Chipset.\n");
149                         break;
150         }
151
152         p += sprintf(p, "------------------------------- General Status ---------------------------------\n");
153         p += sprintf(p, "Burst Mode                           : %sabled\n", (sc1f & 0x01) ? "en" : "dis");
154         p += sprintf(p, "Host Mode                            : %s\n", (sc1f & 0x08) ? "Tri-Stated" : "Normal");
155         p += sprintf(p, "Bus Clocking                         : %s\n",
156                 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
157                 ((sc1f & 0x80) == 0x80) ? "66 External" :
158                 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
159         p += sprintf(p, "IO pad select                        : %s mA\n",
160                 ((sc1c & 0x03) == 0x03) ? "10" :
161                 ((sc1c & 0x02) == 0x02) ? "8" :
162                 ((sc1c & 0x01) == 0x01) ? "6" :
163                 ((sc1c & 0x00) == 0x00) ? "4" : "??");
164         SPLIT_BYTE(sc1e, hi, lo);
165         p += sprintf(p, "Status Polling Period                : %d\n", hi);
166         p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
167         p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
168         p += sprintf(p, "                %s                         %s\n",
169                 (c0&0x80)?"disabled":"enabled ",
170                 (c1&0x80)?"disabled":"enabled ");
171         p += sprintf(p, "66 Clocking     %s                         %s\n",
172                 (sc11&0x02)?"enabled ":"disabled",
173                 (sc11&0x08)?"enabled ":"disabled");
174         p += sprintf(p, "           Mode %s                      Mode %s\n",
175                 (sc1a & 0x01) ? "MASTER" : "PCI   ",
176                 (sc1b & 0x01) ? "MASTER" : "PCI   ");
177         p += sprintf(p, "                %s                     %s\n",
178                 (sc1d & 0x08) ? "Error       " :
179                 ((sc1d & 0x05) == 0x05) ? "Not My INTR " :
180                 (sc1d & 0x04) ? "Interrupting" :
181                 (sc1d & 0x02) ? "FIFO Full   " :
182                 (sc1d & 0x01) ? "FIFO Empty  " : "????????????",
183                 (sc1d & 0x80) ? "Error       " :
184                 ((sc1d & 0x50) == 0x50) ? "Not My INTR " :
185                 (sc1d & 0x40) ? "Interrupting" :
186                 (sc1d & 0x20) ? "FIFO Full   " :
187                 (sc1d & 0x10) ? "FIFO Empty  " : "????????????");
188         p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
189         p += sprintf(p, "DMA enabled:    %s              %s             %s               %s\n",
190                 (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ",(c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
191         p += sprintf(p, "DMA Mode:       %s           %s          %s            %s\n",
192                 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
193                 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
194                 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
195                 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
196         p += sprintf(p, "PIO Mode:       %s            %s           %s            %s\n",
197                 pdc202xx_pio_verbose(reg60h),
198                 pdc202xx_pio_verbose(reg64h),
199                 pdc202xx_pio_verbose(reg68h),
200                 pdc202xx_pio_verbose(reg6ch));
201 #if 0
202         p += sprintf(p, "--------------- Can ATAPI DMA ---------------\n");
203 #endif
204         return (char *)p;
205 }
206
207 static char * pdc202xx_info_new (char *buf, struct pci_dev *dev)
208 {
209         char *p = buf;
210 //      u32 bibma = pci_resource_start(dev, 4);
211
212 //      u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
213 //      u16 reg50h = 0, word88 = 0;
214 //      int udmasel[4]={0,0,0,0}, piosel[4]={0,0,0,0}, i=0, hd=0;
215
216         switch(dev->device) {
217                 case PCI_DEVICE_ID_PROMISE_20275:
218                         p += sprintf(p, "\n                                PDC20275 Chipset.\n");
219                         break;
220                 case PCI_DEVICE_ID_PROMISE_20276:
221                         p += sprintf(p, "\n                                PDC20276 Chipset.\n");
222                         break;
223                 case PCI_DEVICE_ID_PROMISE_20269:
224                         p += sprintf(p, "\n                                PDC20269 TX2 Chipset.\n");
225                         break;
226                 case PCI_DEVICE_ID_PROMISE_20268:
227                 case PCI_DEVICE_ID_PROMISE_20268R:
228                         p += sprintf(p, "\n                                PDC20268 TX2 Chipset.\n");
229                         break;
230 default:
231                         p += sprintf(p, "\n                                PDC202XX Chipset.\n");
232                         break;
233         }
234         return (char *)p;
235 }
236
237 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
238 {
239         char *p = buffer;
240         switch(bmide_dev->device) {
241                 case PCI_DEVICE_ID_PROMISE_20275:
242                 case PCI_DEVICE_ID_PROMISE_20276:
243                 case PCI_DEVICE_ID_PROMISE_20269:
244                 case PCI_DEVICE_ID_PROMISE_20268:
245                 case PCI_DEVICE_ID_PROMISE_20268R:
246                         p = pdc202xx_info_new(buffer, bmide_dev);
247                         break;
248                 default:
249                         p = pdc202xx_info(buffer, bmide_dev);
250                         break;
251         }
252         return p-buffer;        /* => must be less than 4k! */
253 }
254 #endif  /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
255
256 byte pdc202xx_proc = 0;
257
258 const char *pdc_quirk_drives[] = {
259         "QUANTUM FIREBALLlct08 08",
260         "QUANTUM FIREBALLP KA6.4",
261         "QUANTUM FIREBALLP LM20.4",
262         "QUANTUM FIREBALLP KX20.5",
263         "QUANTUM FIREBALLP KX27.3",
264         "QUANTUM FIREBALLP LM20.5",
265         NULL
266 };
267
268 extern char *ide_xfer_verbose (byte xfer_rate);
269
270 /* A Register */
271 #define SYNC_ERRDY_EN   0xC0
272
273 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
274 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
275 #define IORDY_EN        0x20    /* PIO: IOREADY */
276 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
277
278 #define PA3             0x08    /* PIO"A" timing */
279 #define PA2             0x04    /* PIO"A" timing */
280 #define PA1             0x02    /* PIO"A" timing */
281 #define PA0             0x01    /* PIO"A" timing */
282
283 /* B Register */
284
285 #define MB2             0x80    /* DMA"B" timing */
286 #define MB1             0x40    /* DMA"B" timing */
287 #define MB0             0x20    /* DMA"B" timing */
288
289 #define PB4             0x10    /* PIO_FORCE 1:0 */
290
291 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
292 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
293 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
294 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
295
296 /* C Register */
297 #define IORDYp_NO_SPEED 0x4F
298 #define SPEED_DIS       0x0F
299
300 #define DMARQp          0x80
301 #define IORDYp          0x40
302 #define DMAR_EN         0x20
303 #define DMAW_EN         0x10
304
305 #define MC3             0x08    /* DMA"C" timing */
306 #define MC2             0x04    /* DMA"C" timing */
307 #define MC1             0x02    /* DMA"C" timing */
308 #define MC0             0x01    /* DMA"C" timing */
309
310 #if PDC202XX_DECODE_REGISTER_INFO
311
312 #define REG_A           0x01
313 #define REG_B           0x02
314 #define REG_C           0x04
315 #define REG_D           0x08
316
317 static void decode_registers (byte registers, byte value)
318 {
319         byte    bit = 0, bit1 = 0, bit2 = 0;
320
321         switch(registers) {
322                 case REG_A:
323                         bit2 = 0;
324                         printk("A Register ");
325                         if (value & 0x80) printk("SYNC_IN ");
326                         if (value & 0x40) printk("ERRDY_EN ");
327                         if (value & 0x20) printk("IORDY_EN ");
328                         if (value & 0x10) printk("PREFETCH_EN ");
329                         if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
330                         if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
331                         if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
332                         if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
333                         printk("PIO(A) = %d ", bit2);
334                         break;
335                 case REG_B:
336                         bit1 = 0;bit2 = 0;
337                         printk("B Register ");
338                         if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
339                         if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
340                         if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
341                         printk("DMA(B) = %d ", bit1 >> 5);
342                         if (value & 0x10) printk("PIO_FORCED/PB4 ");
343                         if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
344                         if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
345                         if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
346                         if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
347                         printk("PIO(B) = %d ", bit2);
348                         break;
349                 case REG_C:
350                         bit2 = 0;
351                         printk("C Register ");
352                         if (value & 0x80) printk("DMARQp ");
353                         if (value & 0x40) printk("IORDYp ");
354                         if (value & 0x20) printk("DMAR_EN ");
355                         if (value & 0x10) printk("DMAW_EN ");
356
357                         if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
358                         if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
359                         if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
360                         if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
361                         printk("DMA(C) = %d ", bit2);
362                         break;
363                 case REG_D:
364                         printk("D Register ");
365                         break;
366                 default:
367                         return;
368         }
369         printk("\n        %s ", (registers & REG_D) ? "DP" :
370                                 (registers & REG_C) ? "CP" :
371                                 (registers & REG_B) ? "BP" :
372                                 (registers & REG_A) ? "AP" : "ERROR");
373         for (bit=128;bit>0;bit/=2)
374                 printk("%s", (value & bit) ? "1" : "0");
375         printk("\n");
376 }
377
378 #endif /* PDC202XX_DECODE_REGISTER_INFO */
379
380 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
381 {
382         struct hd_driveid *id = drive->id;
383
384         if (pdc_quirk_drives == list) {
385                 while (*list) {
386                         if (strstr(id->model, *list++)) {
387                                 return 2;
388                         }
389                 }
390         } else {
391                 while (*list) {
392                         if (!strcmp(*list++,id->model)) {
393                                 return 1;
394                         }
395                 }
396         }
397         return 0;
398 }
399
400 static int pdc202xx_tune_chipset (ide_drive_t *drive, byte speed)
401 {
402         struct ata_channel *hwif = drive->channel;
403         struct pci_dev *dev = hwif->pci_dev;
404
405         unsigned int            drive_conf;
406         int                     err;
407         byte                    drive_pci, AP, BP, CP, DP;
408         byte                    TA = 0, TB = 0, TC = 0;
409
410         switch (drive->dn) {
411                 case 0: drive_pci = 0x60; break;
412                 case 1: drive_pci = 0x64; break;
413                 case 2: drive_pci = 0x68; break;
414                 case 3: drive_pci = 0x6c; break;
415                 default: return -1;
416         }
417
418         if ((drive->type != ATA_DISK) && (speed < XFER_SW_DMA_0))
419                 return -1;
420
421         pci_read_config_dword(dev, drive_pci, &drive_conf);
422         pci_read_config_byte(dev, (drive_pci), &AP);
423         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
424         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
425         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
426
427 #ifdef CONFIG_BLK_DEV_IDEDMA
428         if (speed >= XFER_SW_DMA_0) {
429                 if ((BP & 0xF0) && (CP & 0x0F)) {
430                         /* clear DMA modes of upper 842 bits of B Register */
431                         /* clear PIO forced mode upper 1 bit of B Register */
432                         pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0xF0);
433                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
434
435                         /* clear DMA modes of lower 8421 bits of C Register */
436                         pci_write_config_byte(dev, (drive_pci)|0x02, CP & ~0x0F);
437                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
438                 }
439         } else {
440 #else
441         {
442 #endif /* CONFIG_BLK_DEV_IDEDMA */
443                 if ((AP & 0x0F) || (BP & 0x07)) {
444                         /* clear PIO modes of lower 8421 bits of A Register */
445                         pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
446                         pci_read_config_byte(dev, (drive_pci), &AP);
447
448                         /* clear PIO modes of lower 421 bits of B Register */
449                         pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
450                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
451
452                         pci_read_config_byte(dev, (drive_pci), &AP);
453                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
454                 }
455         }
456
457         pci_read_config_byte(dev, (drive_pci), &AP);
458         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
459         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
460
461         switch(speed) {
462 #ifdef CONFIG_BLK_DEV_IDEDMA
463                 /* case XFER_UDMA_6: */
464                 case XFER_UDMA_5:
465                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;    /* speed 8 == UDMA mode 4 */
466                 case XFER_UDMA_3:       TB = 0x40; TC = 0x02; break;    /* speed 7 == UDMA mode 3 */
467                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;    /* speed 6 == UDMA mode 2 */
468                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;    /* speed 5 == UDMA mode 1 */
469                 case XFER_UDMA_0:       TB = 0x60; TC = 0x03; break;    /* speed 4 == UDMA mode 0 */
470                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;    /* speed 4 == MDMA mode 2 */
471                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;    /* speed 3 == MDMA mode 1 */
472                 case XFER_MW_DMA_0:     TB = 0x60; TC = 0x05; break;    /* speed 2 == MDMA mode 0 */
473                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;    /* speed 0 == SDMA mode 2 */
474                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;    /* speed 1 == SDMA mode 1 */
475                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;    /* speed 0 == SDMA mode 0 */
476 #endif /* CONFIG_BLK_DEV_IDEDMA */
477                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
478                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
479                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
480                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
481                 case XFER_PIO_0:
482                 default:                TA = 0x09; TB = 0x13; break;
483         }
484
485 #ifdef CONFIG_BLK_DEV_IDEDMA
486         if (speed >= XFER_SW_DMA_0) {
487                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
488                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
489         } else {
490 #else
491         {
492 #endif /* CONFIG_BLK_DEV_IDEDMA */
493                 pci_write_config_byte(dev, (drive_pci), AP|TA);
494                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
495         }
496
497 #if PDC202XX_DECODE_REGISTER_INFO
498         pci_read_config_byte(dev, (drive_pci), &AP);
499         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
500         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
501         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
502
503         decode_registers(REG_A, AP);
504         decode_registers(REG_B, BP);
505         decode_registers(REG_C, CP);
506         decode_registers(REG_D, DP);
507 #endif /* PDC202XX_DECODE_REGISTER_INFO */
508
509         if (!drive->init_speed)
510                 drive->init_speed = speed;
511         err = ide_config_drive_speed(drive, speed);
512         drive->current_speed = speed;
513
514 #if PDC202XX_DEBUG_DRIVE_INFO
515         printk("%s: %s drive%d 0x%08x ",
516                 drive->name, ide_xfer_verbose(speed),
517                 drive->dn, drive_conf);
518                 pci_read_config_dword(dev, drive_pci, &drive_conf);
519         printk("0x%08x\n", drive_conf);
520 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
521         return err;
522 }
523
524 static int pdc202xx_new_tune_chipset (ide_drive_t *drive, byte speed)
525 {
526         struct ata_channel *hwif = drive->channel;
527 #ifdef CONFIG_BLK_DEV_IDEDMA
528         unsigned long indexreg  = (hwif->dma_base + 1);
529         unsigned long datareg   = (hwif->dma_base + 3);
530 #else
531         struct pci_dev *dev     = hwif->pci_dev;
532         unsigned long high_16   = pci_resource_start(dev, 4);
533         unsigned long indexreg  = high_16 + (hwif->unit ? 0x09 : 0x01);
534         unsigned long datareg   = (indexreg + 2);
535 #endif /* CONFIG_BLK_DEV_IDEDMA */
536         byte thold              = 0x10;
537         byte adj                = (drive->dn%2) ? 0x08 : 0x00;
538
539         int                     err;
540
541 #ifdef CONFIG_BLK_DEV_IDEDMA
542         if (speed == XFER_UDMA_2) {
543                 OUT_BYTE((thold + adj), indexreg);
544                 OUT_BYTE((IN_BYTE(datareg) & 0x7f), datareg);
545         }
546         switch (speed) {
547                 case XFER_UDMA_7:
548                         speed = XFER_UDMA_6;
549                 case XFER_UDMA_6:
550                         OUT_BYTE((0x10 + adj), indexreg);
551                         OUT_BYTE(0x1a, datareg);
552                         OUT_BYTE((0x11 + adj), indexreg);
553                         OUT_BYTE(0x01, datareg);
554                         OUT_BYTE((0x12 + adj), indexreg);
555                         OUT_BYTE(0xcb, datareg);
556                         break;
557                 case XFER_UDMA_5:
558                         OUT_BYTE((0x10 + adj), indexreg);
559                         OUT_BYTE(0x1a, datareg);
560                         OUT_BYTE((0x11 + adj), indexreg);
561                         OUT_BYTE(0x02, datareg);
562                         OUT_BYTE((0x12 + adj), indexreg);
563                         OUT_BYTE(0xcb, datareg);
564                         break;
565                 case XFER_UDMA_4:
566                         OUT_BYTE((0x10 + adj), indexreg);
567                         OUT_BYTE(0x1a, datareg);
568                         OUT_BYTE((0x11 + adj), indexreg);
569                         OUT_BYTE(0x03, datareg);
570                         OUT_BYTE((0x12 + adj), indexreg);
571                         OUT_BYTE(0xcd, datareg);
572                         break;
573                 case XFER_UDMA_3:
574                         OUT_BYTE((0x10 + adj), indexreg);
575                         OUT_BYTE(0x1a, datareg);
576                         OUT_BYTE((0x11 + adj), indexreg);
577                         OUT_BYTE(0x05, datareg);
578                         OUT_BYTE((0x12 + adj), indexreg);
579                         OUT_BYTE(0xcd, datareg);
580                         break;
581                 case XFER_UDMA_2:
582                         OUT_BYTE((0x10 + adj), indexreg);
583                         OUT_BYTE(0x2a, datareg);
584                         OUT_BYTE((0x11 + adj), indexreg);
585                         OUT_BYTE(0x07, datareg);
586                         OUT_BYTE((0x12 + adj), indexreg);
587                         OUT_BYTE(0xcd, datareg);
588                         break;
589                 case XFER_UDMA_1:
590                         OUT_BYTE((0x10 + adj), indexreg);
591                         OUT_BYTE(0x3a, datareg);
592                         OUT_BYTE((0x11 + adj), indexreg);
593                         OUT_BYTE(0x0a, datareg);
594                         OUT_BYTE((0x12 + adj), indexreg);
595                         OUT_BYTE(0xd0, datareg);
596                         break;
597                 case XFER_UDMA_0:
598                         OUT_BYTE((0x10 + adj), indexreg);
599                         OUT_BYTE(0x4a, datareg);
600                         OUT_BYTE((0x11 + adj), indexreg);
601                         OUT_BYTE(0x0f, datareg);
602                         OUT_BYTE((0x12 + adj), indexreg);
603                         OUT_BYTE(0xd5, datareg);
604                         break;
605                 case XFER_MW_DMA_2:
606                         OUT_BYTE((0x0e + adj), indexreg);
607                         OUT_BYTE(0x69, datareg);
608                         OUT_BYTE((0x0f + adj), indexreg);
609                         OUT_BYTE(0x25, datareg);
610                         break;
611                 case XFER_MW_DMA_1:
612                         OUT_BYTE((0x0e + adj), indexreg);
613                         OUT_BYTE(0x6b, datareg);
614                         OUT_BYTE((0x0f+ adj), indexreg);
615                         OUT_BYTE(0x27, datareg);
616                         break;
617                 case XFER_MW_DMA_0:
618                         OUT_BYTE((0x0e + adj), indexreg);
619                         OUT_BYTE(0xdf, datareg);
620                         OUT_BYTE((0x0f + adj), indexreg);
621                         OUT_BYTE(0x5f, datareg);
622                         break;
623 #else
624         switch (speed) {
625 #endif /* CONFIG_BLK_DEV_IDEDMA */
626                 case XFER_PIO_4:
627                         OUT_BYTE((0x0c + adj), indexreg);
628                         OUT_BYTE(0x23, datareg);
629                         OUT_BYTE((0x0d + adj), indexreg);
630                         OUT_BYTE(0x09, datareg);
631                         OUT_BYTE((0x13 + adj), indexreg);
632                         OUT_BYTE(0x25, datareg);
633                         break;
634                 case XFER_PIO_3:
635                         OUT_BYTE((0x0c + adj), indexreg);
636                         OUT_BYTE(0x27, datareg);
637                         OUT_BYTE((0x0d + adj), indexreg);
638                         OUT_BYTE(0x0d, datareg);
639                         OUT_BYTE((0x13 + adj), indexreg);
640                         OUT_BYTE(0x35, datareg);
641                         break;
642                 case XFER_PIO_2:
643                         OUT_BYTE((0x0c + adj), indexreg);
644                         OUT_BYTE(0x23, datareg);
645                         OUT_BYTE((0x0d + adj), indexreg);
646                         OUT_BYTE(0x26, datareg);
647                         OUT_BYTE((0x13 + adj), indexreg);
648                         OUT_BYTE(0x64, datareg);
649                         break;
650                 case XFER_PIO_1:
651                         OUT_BYTE((0x0c + adj), indexreg);
652                         OUT_BYTE(0x46, datareg);
653                         OUT_BYTE((0x0d + adj), indexreg);
654                         OUT_BYTE(0x29, datareg);
655                         OUT_BYTE((0x13 + adj), indexreg);
656                         OUT_BYTE(0xa4, datareg);
657                         break;
658                 case XFER_PIO_0:
659                         OUT_BYTE((0x0c + adj), indexreg);
660                         OUT_BYTE(0xfb, datareg);
661                         OUT_BYTE((0x0d + adj), indexreg);
662                         OUT_BYTE(0x2b, datareg);
663                         OUT_BYTE((0x13 + adj), indexreg);
664                         OUT_BYTE(0xac, datareg);
665                         break;
666                 default:
667                         ;
668         }
669
670         if (!drive->init_speed)
671                 drive->init_speed = speed;
672         err = ide_config_drive_speed(drive, speed);
673         drive->current_speed = speed;
674
675         return err;
676 }
677
678 /*   0    1    2    3    4    5    6   7   8
679  * 960, 480, 390, 300, 240, 180, 120, 90, 60
680  *           180, 150, 120,  90,  60
681  * DMA_Speed
682  * 180, 120,  90,  90,  90,  60,  30
683  *  11,   5,   4,   3,   2,   1,   0
684  */
685 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
686 {
687         byte speed = 0x00;
688
689         if (pio == 255)
690                 speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
691         else
692                 speed = XFER_PIO_0 + min_t(byte, pio, 4);
693
694         return ((int) pdc202xx_tune_chipset(drive, speed));
695 }
696
697 static void pdc202xx_tune_drive (ide_drive_t *drive, byte pio)
698 {
699         (void) config_chipset_for_pio(drive, pio);
700 }
701
702 #ifdef CONFIG_BLK_DEV_IDEDMA
703 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
704 {
705         struct hd_driveid *id   = drive->id;
706         struct ata_channel *hwif = drive->channel;
707         struct pci_dev *dev     = hwif->pci_dev;
708         unsigned long high_16   = pci_resource_start(dev, 4);
709         unsigned long dma_base  = hwif->dma_base;
710         unsigned long indexreg  = dma_base + 1;
711         unsigned long datareg   = dma_base + 3;
712         byte iordy              = 0x13;
713         byte adj                = (drive->dn%2) ? 0x08 : 0x00;
714         byte cable              = 0;
715         byte jumpbit            = 0;
716         byte unit               = (drive->select.b.unit & 0x01);
717         unsigned int            drive_conf;
718         byte                    drive_pci = 0;
719         byte                    test1, test2, speed = -1;
720         byte                    AP;
721         unsigned short          EP;
722         byte CLKSPD             = 0;
723         byte udma_33            = ultra;
724 //      byte udma_33            = ultra ? (IN_BYTE(high_16 + 0x001f) & 1) : 0;
725         byte udma_66            = ((eighty_ninty_three(drive)) && udma_33) ? 1 : 0;
726         byte udma_100           = 0;
727         byte udma_133           = 0;
728         byte mask               = hwif->unit ? 0x08 : 0x02;
729         unsigned short c_mask   = hwif->unit ? (1<<11) : (1<<10);
730
731         byte ultra_66           = ((id->dma_ultra & 0x0010) ||
732                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
733         byte ultra_100          = ((id->dma_ultra & 0x0020) ||
734                                    (ultra_66)) ? 1 : 0;
735         byte ultra_133          = ((id->dma_ultra & 0x0040) ||
736                                    (ultra_100)) ? 1 : 0;
737
738         switch(dev->device) {
739                 case PCI_DEVICE_ID_PROMISE_20275:
740                 case PCI_DEVICE_ID_PROMISE_20276:
741                 case PCI_DEVICE_ID_PROMISE_20269:
742                         udma_133 = (udma_66) ? 1 : 0;
743                         udma_100 = (udma_66) ? 1 : 0;
744                         OUT_BYTE(0x0b, (hwif->dma_base + 1));
745                         cable = ((IN_BYTE((hwif->dma_base + 3)) & 0x04));
746                         jumpbit = 1;
747                         break;
748                 case PCI_DEVICE_ID_PROMISE_20268R:
749                         udma_100 = 1;
750                         udma_66 = 1;
751                         OUT_BYTE(0x0b, (hwif->dma_base + 1));
752                         cable = ((IN_BYTE((hwif->dma_base + 3)) & 0x04));
753                         jumpbit = 1;
754                         break;
755                 case PCI_DEVICE_ID_PROMISE_20268:
756                         udma_100 = (udma_66) ? 1 : 0;
757                         OUT_BYTE(0x0b, (hwif->dma_base + 1));
758                         cable = ((IN_BYTE((hwif->dma_base + 3)) & 0x04));
759                         jumpbit = 1;
760                         break;
761                 case PCI_DEVICE_ID_PROMISE_20267:
762                 case PCI_DEVICE_ID_PROMISE_20265:
763                         udma_100 = (udma_66) ? 1 : 0;
764                         pci_read_config_word(dev, 0x50, &EP);
765                         cable = (EP & c_mask);
766                         jumpbit = 0;
767                         break;
768                 case PCI_DEVICE_ID_PROMISE_20262:
769                         pci_read_config_word(dev, 0x50, &EP);
770                         cable = (EP & c_mask);
771                         jumpbit = 0;
772                         break;
773                 default:
774                         udma_100 = 0; udma_133 = 0; cable = 1; jumpbit = 0;
775                         break;
776         }
777
778         if (!jumpbit)
779                 CLKSPD = IN_BYTE(high_16 + 0x11);
780         /*
781          * Set the control register to use the 66Mhz system
782          * clock for UDMA 3/4 mode operation. If one drive on
783          * a channel is U66 capable but the other isn't we
784          * fall back to U33 mode. The BIOS INT 13 hooks turn
785          * the clock on then off for each read/write issued. I don't
786          * do that here because it would require modifying the
787          * kernel, seperating the fop routines from the kernel or
788          * somehow hooking the fops calls. It may also be possible to
789          * leave the 66Mhz clock on and readjust the timing
790          * parameters.
791          */
792
793         if (((ultra_66) || (ultra_100) || (ultra_133)) && (cable)) {
794 #ifdef DEBUG
795                 printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->unit ? "Secondary" : "Primary");
796                 printk("         Switching to Ultra33 mode.\n");
797 #endif /* DEBUG */
798                 /* Primary   : zero out second bit */
799                 /* Secondary : zero out fourth bit */
800                 if (!jumpbit)
801                         OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
802                 printk("Warning: %s channel requires an 80-pin cable for operation.\n", hwif->unit ? "Secondary":"Primary");
803                 printk("%s reduced to Ultra33 mode.\n", drive->name);
804                 udma_66 = 0; udma_100 = 0; udma_133 = 0;
805         } else {
806                 if ((ultra_66) || (ultra_100) || (ultra_133)) {
807                         /*
808                          * check to make sure drive on same channel
809                          * is u66 capable
810                          */
811                         if (hwif->drives[!(drive->dn%2)].id) {
812                                 if ((hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0040) ||
813                                     (hwif->drives[!(drive->dn%2)].id->dma_ultra
814 & 0x0020) ||
815                                     (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0010) ||
816                                     (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0008)) {
817                                         if (!jumpbit)
818                                                 OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
819                                 } else {
820                                         if (!jumpbit)
821                                                 OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
822                                 }
823                         } else { /* udma4 drive by itself */
824                                 if (!jumpbit)
825                                         OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
826                         }
827                 }
828         }
829
830         if (jumpbit) {
831                 if (drive->type != ATA_DISK)
832                         return ide_dma_off_quietly;
833                 if (id->capability & 4) {       /* IORDY_EN & PREFETCH_EN */
834                         OUT_BYTE((iordy + adj), indexreg);
835                         OUT_BYTE((IN_BYTE(datareg)|0x03), datareg);
836                 }
837                 goto jumpbit_is_set;
838         }
839
840         switch(drive->dn) {
841                 case 0: drive_pci = 0x60;
842                         pci_read_config_dword(dev, drive_pci, &drive_conf);
843                         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
844                                 goto chipset_is_set;
845                         pci_read_config_byte(dev, (drive_pci), &test1);
846                         if (!(test1 & SYNC_ERRDY_EN))
847                                 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
848                         break;
849                 case 1: drive_pci = 0x64;
850                         pci_read_config_dword(dev, drive_pci, &drive_conf);
851                         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
852                                 goto chipset_is_set;
853                         pci_read_config_byte(dev, 0x60, &test1);
854                         pci_read_config_byte(dev, (drive_pci), &test2);
855                         if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
856                                 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
857                         break;
858                 case 2: drive_pci = 0x68;
859                         pci_read_config_dword(dev, drive_pci, &drive_conf);
860                         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
861                                 goto chipset_is_set;
862                         pci_read_config_byte(dev, (drive_pci), &test1);
863                         if (!(test1 & SYNC_ERRDY_EN))
864                                 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
865                         break;
866                 case 3: drive_pci = 0x6c;
867                         pci_read_config_dword(dev, drive_pci, &drive_conf);
868                         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
869                                 goto chipset_is_set;
870                         pci_read_config_byte(dev, 0x68, &test1);
871                         pci_read_config_byte(dev, (drive_pci), &test2);
872                         if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
873                                 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
874                         break;
875                 default:
876                         return ide_dma_off;
877         }
878
879 chipset_is_set:
880
881         if (drive->type != ATA_DISK)
882                 return ide_dma_off_quietly;
883
884         pci_read_config_byte(dev, (drive_pci), &AP);
885         if (id->capability & 4) /* IORDY_EN */
886                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
887         pci_read_config_byte(dev, (drive_pci), &AP);
888         if (drive->type == ATA_DISK)    /* PREFETCH_EN */
889                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
890
891 jumpbit_is_set:
892
893         if ((id->dma_ultra & 0x0040)&&(udma_133))       speed = XFER_UDMA_6;
894         else if ((id->dma_ultra & 0x0020)&&(udma_100))  speed = XFER_UDMA_5;
895         else if ((id->dma_ultra & 0x0010)&&(udma_66))   speed = XFER_UDMA_4;
896         else if ((id->dma_ultra & 0x0008)&&(udma_66))   speed = XFER_UDMA_3;
897         else if ((id->dma_ultra & 0x0004)&&(udma_33))   speed = XFER_UDMA_2;
898         else if ((id->dma_ultra & 0x0002)&&(udma_33))   speed = XFER_UDMA_1;
899         else if ((id->dma_ultra & 0x0001)&&(udma_33))   speed = XFER_UDMA_0;
900         else if (id->dma_mword & 0x0004)                speed = XFER_MW_DMA_2;
901         else if (id->dma_mword & 0x0002)                speed = XFER_MW_DMA_1;
902         else if (id->dma_mword & 0x0001)                speed = XFER_MW_DMA_0;
903         else if ((id->dma_1word & 0x0004)&&(!jumpbit))  speed = XFER_SW_DMA_2;
904         else if ((id->dma_1word & 0x0002)&&(!jumpbit))  speed = XFER_SW_DMA_1;
905         else if ((id->dma_1word & 0x0001)&&(!jumpbit))  speed = XFER_SW_DMA_0;
906         else {
907                 /* restore original pci-config space */
908                 if (!jumpbit)
909                         pci_write_config_dword(dev, drive_pci, drive_conf);
910                 return ide_dma_off_quietly;
911         }
912
913         outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
914         (void) hwif->speedproc(drive, speed);
915
916         return ((int)   ((id->dma_ultra >> 14) & 3) ? ide_dma_on :
917                         ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
918                         ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
919                         ((id->dma_mword >> 8) & 7) ? ide_dma_on : 
920                         ((id->dma_1word >> 8) & 7) ? ide_dma_on :
921                                                      ide_dma_off_quietly);
922 }
923
924 static int config_drive_xfer_rate (ide_drive_t *drive)
925 {
926         struct hd_driveid *id = drive->id;
927         struct ata_channel *hwif = drive->channel;
928         ide_dma_action_t dma_func = ide_dma_off_quietly;
929
930         if (id && (id->capability & 1) && hwif->autodma) {
931                 /* Consult the list of known "bad" drives */
932                 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
933                         dma_func = ide_dma_off;
934                         goto fast_ata_pio;
935                 }
936                 dma_func = ide_dma_off_quietly;
937                 if (id->field_valid & 4) {
938                         if (id->dma_ultra & 0x007F) {
939                                 /* Force if Capable UltraDMA */
940                                 dma_func = config_chipset_for_dma(drive, 1);
941                                 if ((id->field_valid & 2) &&
942                                     (dma_func != ide_dma_on))
943                                         goto try_dma_modes;
944                         }
945                 } else if (id->field_valid & 2) {
946 try_dma_modes:
947                         if ((id->dma_mword & 0x0007) ||
948                             (id->dma_1word & 0x0007)) {
949                                 /* Force if Capable regular DMA modes */
950                                 dma_func = config_chipset_for_dma(drive, 0);
951                                 if (dma_func != ide_dma_on)
952                                         goto no_dma_set;
953                         }
954                 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
955                         if (id->eide_dma_time > 150) {
956                                 goto no_dma_set;
957                         }
958                         /* Consult the list of known "good" drives */
959                         dma_func = config_chipset_for_dma(drive, 0);
960                         if (dma_func != ide_dma_on)
961                                 goto no_dma_set;
962                 } else {
963                         goto fast_ata_pio;
964                 }
965         } else if ((id->capability & 8) || (id->field_valid & 2)) {
966 fast_ata_pio:
967                 dma_func = ide_dma_off_quietly;
968 no_dma_set:
969                 (void) config_chipset_for_pio(drive, 5);
970         }
971
972         return drive->channel->dmaproc(dma_func, drive);
973 }
974
975 int pdc202xx_quirkproc (ide_drive_t *drive)
976 {
977         return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
978 }
979
980 /*
981  * pdc202xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
982  */
983 int pdc202xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
984 {
985         byte dma_stat           = 0;
986         byte sc1d               = 0;
987         byte newchip            = 0;
988         byte clock              = 0;
989         byte hardware48hack     = 0;
990         struct ata_channel *hwif = drive->channel;
991         struct pci_dev *dev     = hwif->pci_dev;
992         unsigned long high_16   = pci_resource_start(dev, 4);
993         unsigned long atapi_reg = high_16 + (hwif->unit ? 0x24 : 0x00);
994         unsigned long dma_base  = hwif->dma_base;
995
996         switch (dev->device) {
997                 case PCI_DEVICE_ID_PROMISE_20275:
998                 case PCI_DEVICE_ID_PROMISE_20276:
999                 case PCI_DEVICE_ID_PROMISE_20269:
1000                 case PCI_DEVICE_ID_PROMISE_20268R:
1001                 case PCI_DEVICE_ID_PROMISE_20268:
1002                         newchip = 1;
1003                         break;
1004                 case PCI_DEVICE_ID_PROMISE_20267:
1005                 case PCI_DEVICE_ID_PROMISE_20265:
1006                 case PCI_DEVICE_ID_PROMISE_20262:
1007                         hardware48hack = 1;
1008                         clock = IN_BYTE(high_16 + 0x11);
1009                 default:
1010                         break;
1011         }
1012
1013         switch (func) {
1014                 case ide_dma_check:
1015                         return config_drive_xfer_rate(drive);
1016                 case ide_dma_begin:
1017                         /* Note that this is done *after* the cmd has
1018                          * been issued to the drive, as per the BM-IDE spec.
1019                          * The Promise Ultra33 doesn't work correctly when
1020                          * we do this part before issuing the drive cmd.
1021                          */
1022                         if ((drive->addressing) && (hardware48hack)) {
1023                                 struct request *rq = HWGROUP(drive)->rq;
1024                                 unsigned long word_count = 0;
1025
1026                                 outb(clock|(hwif->unit ? 0x08 : 0x02), high_16 + 0x11);
1027                                 word_count = (rq->nr_sectors << 8);
1028                                 word_count = (rq_data_dir(rq) == READ) ? word_count | 0x05000000 : word_count | 0x06000000;
1029                                 outl(word_count, atapi_reg);
1030                         }
1031                         break;
1032                 case ide_dma_end:
1033                         if ((drive->addressing) && (hardware48hack)) {
1034                                 outl(0, atapi_reg);     /* zero out extra */
1035                                 clock = IN_BYTE(high_16 + 0x11);
1036                                 OUT_BYTE(clock & ~(hwif->unit ? 0x08:0x02), high_16 + 0x11);
1037                         }
1038                         break;
1039                 case ide_dma_test_irq:  /* returns 1 if dma irq issued, 0 otherwise */
1040                         dma_stat = IN_BYTE(dma_base+2);
1041                         if (newchip)
1042                                 return (dma_stat & 4) == 4;
1043
1044                         sc1d = IN_BYTE(high_16 + 0x001d);
1045                         if (drive->channel->unit) {
1046                                 if ((sc1d & 0x50) == 0x50) goto somebody_else;
1047                                 else if ((sc1d & 0x40) == 0x40)
1048                                         return (dma_stat & 4) == 4;
1049                         } else {
1050                                 if ((sc1d & 0x05) == 0x05) goto somebody_else;
1051                                 else if ((sc1d & 0x04) == 0x04)
1052                                         return (dma_stat & 4) == 4;
1053                         }
1054 somebody_else:
1055                         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
1056                 case ide_dma_lostirq:
1057                 case ide_dma_timeout:
1058                         if (drive->channel->resetproc != NULL)
1059                                 drive->channel->resetproc(drive);
1060                 default:
1061                         break;
1062         }
1063         return ide_dmaproc(func, drive);        /* use standard DMA stuff */
1064 }
1065 #endif /* CONFIG_BLK_DEV_IDEDMA */
1066
1067 void pdc202xx_new_reset (ide_drive_t *drive)
1068 {
1069         OUT_BYTE(0x04,IDE_CONTROL_REG);
1070         mdelay(1000);
1071         OUT_BYTE(0x00,IDE_CONTROL_REG);
1072         mdelay(1000);
1073         printk("PDC202XX: %s channel reset.\n",
1074                 drive->channel->unit ? "Secondary" : "Primary");
1075 }
1076
1077 void pdc202xx_reset (ide_drive_t *drive)
1078 {
1079         unsigned long high_16   = pci_resource_start(drive->channel->pci_dev, 4);
1080         byte udma_speed_flag    = IN_BYTE(high_16 + 0x001f);
1081
1082         OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
1083         mdelay(100);
1084         OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
1085         mdelay(2000);           /* 2 seconds ?! */
1086         printk("PDC202XX: %s channel reset.\n",
1087                 drive->channel->unit ? "Secondary" : "Primary");
1088 }
1089
1090 /*
1091  * Since SUN Cobalt is attempting to do this operation, I should disclose
1092  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1093  * HOTSWAP ATA Infrastructure.
1094  */
1095 static int pdc202xx_tristate (ide_drive_t * drive, int state)
1096 {
1097 #if 0
1098         struct ata_channel *hwif = drive->channel;
1099         unsigned long high_16   = pci_resource_start(hwif->pci_dev, 4);
1100         byte sc1f               = inb(high_16 + 0x001f);
1101
1102         if (!hwif)
1103                 return -EINVAL;
1104
1105 //      hwif->bus_state = state;
1106
1107         if (state) {
1108                 outb(sc1f | 0x08, high_16 + 0x001f);
1109         } else {
1110                 outb(sc1f & ~0x08, high_16 + 0x001f);
1111         }
1112 #endif
1113         return 0;
1114 }
1115
1116 unsigned int __init pci_init_pdc202xx(struct pci_dev *dev)
1117 {
1118         unsigned long high_16   = pci_resource_start(dev, 4);
1119         byte udma_speed_flag    = IN_BYTE(high_16 + 0x001f);
1120         byte primary_mode       = IN_BYTE(high_16 + 0x001a);
1121         byte secondary_mode     = IN_BYTE(high_16 + 0x001b);
1122         byte newchip            = 0;
1123
1124         if (dev->resource[PCI_ROM_RESOURCE].start) {
1125                 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1126                 printk("%s: ROM enabled at 0x%08lx\n", dev->name, dev->resource[PCI_ROM_RESOURCE].start);
1127         }
1128
1129         switch (dev->device) {
1130                 case PCI_DEVICE_ID_PROMISE_20275:
1131                 case PCI_DEVICE_ID_PROMISE_20276:
1132                 case PCI_DEVICE_ID_PROMISE_20269:
1133                 case PCI_DEVICE_ID_PROMISE_20268R:
1134                 case PCI_DEVICE_ID_PROMISE_20268:
1135                         newchip = 1;
1136                         break;
1137                 case PCI_DEVICE_ID_PROMISE_20267:
1138                 case PCI_DEVICE_ID_PROMISE_20265:
1139                         OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
1140                         mdelay(100);
1141                         OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
1142                         mdelay(2000);   /* 2 seconds ?! */
1143                         break;
1144                 case PCI_DEVICE_ID_PROMISE_20262:
1145                         /*
1146                          * software reset -  this is required because the bios
1147                          * will set UDMA timing on if the hdd supports it. The
1148                          * user may want to turn udma off. A bug in the pdc20262
1149                          * is that it cannot handle a downgrade in timing from
1150                          * UDMA to DMA. Disk accesses after issuing a set
1151                          * feature command will result in errors. A software
1152                          * reset leaves the timing registers intact,
1153                          * but resets the drives.
1154                          */
1155                         OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
1156                         mdelay(100);
1157                         OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
1158                         mdelay(2000);   /* 2 seconds ?! */
1159                 default:
1160                         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
1161                                 byte irq = 0, irq2 = 0;
1162                                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1163                                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);    /* 0xbc */
1164                                 if (irq != irq2) {
1165                                         pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
1166                                         printk("%s: pci-config space interrupt mirror fixed.\n", dev->name);
1167                                 }
1168                         }
1169                         break;
1170         }
1171
1172         if (newchip)
1173                 goto fttk_tx_series;
1174
1175         printk("%s: (U)DMA Burst Bit %sABLED " \
1176                 "Primary %s Mode " \
1177                 "Secondary %s Mode.\n",
1178                 dev->name,
1179                 (udma_speed_flag & 1) ? "EN" : "DIS",
1180                 (primary_mode & 1) ? "MASTER" : "PCI",
1181                 (secondary_mode & 1) ? "MASTER" : "PCI" );
1182
1183 #ifdef CONFIG_PDC202XX_BURST
1184         if (!(udma_speed_flag & 1)) {
1185                 printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", dev->name, udma_speed_flag, (udma_speed_flag|1));
1186                 OUT_BYTE(udma_speed_flag|1, high_16 + 0x001f);
1187                 printk("%sCTIVE\n", (IN_BYTE(high_16 + 0x001f) & 1) ? "A" : "INA");
1188         }
1189 #endif /* CONFIG_PDC202XX_BURST */
1190
1191 #ifdef CONFIG_PDC202XX_MASTER
1192         if (!(primary_mode & 1)) {
1193                 printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
1194                         dev->name, primary_mode, (primary_mode|1));
1195                 OUT_BYTE(primary_mode|1, high_16 + 0x001a);
1196                 printk("%s\n", (IN_BYTE(high_16 + 0x001a) & 1) ? "MASTER" : "PCI");
1197         }
1198
1199         if (!(secondary_mode & 1)) {
1200                 printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
1201                         dev->name, secondary_mode, (secondary_mode|1));
1202                 OUT_BYTE(secondary_mode|1, high_16 + 0x001b);
1203                 printk("%s\n", (IN_BYTE(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
1204         }
1205 #endif /* CONFIG_PDC202XX_MASTER */
1206
1207 fttk_tx_series:
1208
1209 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
1210         if (!pdc202xx_proc) {
1211                 pdc202xx_proc = 1;
1212                 bmide_dev = dev;
1213                 pdc202xx_display_info = &pdc202xx_get_info;
1214         }
1215 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
1216         return dev->irq;
1217 }
1218
1219 unsigned int __init ata66_pdc202xx(struct ata_channel *hwif)
1220 {
1221         unsigned short mask = (hwif->unit) ? (1<<11) : (1<<10);
1222         unsigned short CIS;
1223
1224         switch(hwif->pci_dev->device) {
1225                 case PCI_DEVICE_ID_PROMISE_20275:
1226                 case PCI_DEVICE_ID_PROMISE_20276:
1227                 case PCI_DEVICE_ID_PROMISE_20269:
1228                 case PCI_DEVICE_ID_PROMISE_20268:
1229                 case PCI_DEVICE_ID_PROMISE_20268R:
1230                         OUT_BYTE(0x0b, (hwif->dma_base + 1));
1231                         return (!(IN_BYTE((hwif->dma_base + 3)) & 0x04));
1232                 default:
1233                         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
1234                         return (!(CIS & mask));
1235         }
1236 }
1237
1238 void __init ide_init_pdc202xx(struct ata_channel *hwif)
1239 {
1240         hwif->tuneproc  = &pdc202xx_tune_drive;
1241         hwif->quirkproc = &pdc202xx_quirkproc;
1242
1243         switch(hwif->pci_dev->device) {
1244                 case PCI_DEVICE_ID_PROMISE_20275:
1245                 case PCI_DEVICE_ID_PROMISE_20276:
1246                 case PCI_DEVICE_ID_PROMISE_20269:
1247                 case PCI_DEVICE_ID_PROMISE_20268:
1248                 case PCI_DEVICE_ID_PROMISE_20268R:
1249                         hwif->speedproc = &pdc202xx_new_tune_chipset;
1250                         hwif->resetproc = &pdc202xx_new_reset;
1251                         break;
1252                 case PCI_DEVICE_ID_PROMISE_20267:
1253                 case PCI_DEVICE_ID_PROMISE_20265:
1254                 case PCI_DEVICE_ID_PROMISE_20262:
1255                         hwif->busproc   = &pdc202xx_tristate;
1256                         hwif->resetproc = &pdc202xx_reset;
1257                 case PCI_DEVICE_ID_PROMISE_20246:
1258                         hwif->speedproc = &pdc202xx_tune_chipset;
1259                 default:
1260                         break;
1261         }
1262
1263 #undef CONFIG_PDC202XX_32_UNMASK
1264 #ifdef CONFIG_PDC202XX_32_UNMASK
1265         hwif->drives[0].io_32bit = 1;
1266         hwif->drives[1].io_32bit = 1;
1267         hwif->drives[0].unmask = 1;
1268         hwif->drives[1].unmask = 1;
1269 #endif /* CONFIG_PDC202XX_32_UNMASK */
1270
1271 #ifdef CONFIG_BLK_DEV_IDEDMA
1272         if (hwif->dma_base) {
1273                 hwif->dmaproc = &pdc202xx_dmaproc;
1274                 hwif->highmem = 1;
1275                 if (!noautodma)
1276                         hwif->autodma = 1;
1277         } else {
1278                 hwif->drives[0].autotune = 1;
1279                 hwif->drives[1].autotune = 1;
1280                 hwif->autodma = 0;
1281         }
1282 #else /* !CONFIG_BLK_DEV_IDEDMA */
1283         hwif->drives[0].autotune = 1;
1284         hwif->drives[1].autotune = 1;
1285         hwif->autodma = 0;
1286 #endif /* CONFIG_BLK_DEV_IDEDMA */
1287 }