rowboat:dvachevs-dvachevs-u-boot.git
7 years agoTI816x: NOR: Do not use delay after ddr init in case of NOR boot ti81xx-master
Basheer, Mansoor Ahamed [Fri, 8 Jul 2011 06:08:55 +0000 (11:38 +0530)]
TI816x: NOR: Do not use delay after ddr init in case of NOR boot

 We added 50ms delay in four places for ddr3 initialization issue.
 This increased the boot time for NOR boot to 40 secs.
 In case of NOR boot, we use XIP and this has inherent delay.
 Hence, there is no need for explicit delay in NOR boot.
 This additional delay increased the boot time.

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
7 years agoTI8168 : Fixed the ti8168 DDR3 @800MHz stability issue
Raj, Deepu [Thu, 7 Jul 2011 13:58:50 +0000 (19:28 +0530)]
TI8168 : Fixed the ti8168 DDR3 @800MHz stability issue

Added a 50ms delay between DDR init and DDR relocation
 That fixed the ti8168 DDR3 @880MHz stability issue

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
7 years agoti814x: wdt: Stop and unfreeze WDT
Saxena, Parth [Wed, 29 Jun 2011 12:49:05 +0000 (18:19 +0530)]
ti814x: wdt: Stop and unfreeze WDT

This patch stops and unfreezes the non-secure  watchdog timer
in TI814x.
Once this is done, the kernel driver can use the watchdog
normally.

Signed-off-by: Saxena, Parth <parth.saxena@ti.com>
7 years agotiimage: Remove padding for ti814x
Vaibhav Bedia [Wed, 29 Jun 2011 09:58:54 +0000 (15:28 +0530)]
tiimage: Remove padding for ti814x

First stage of TI814x had a padding of 12K to accomodate the stack
when running out of internal memory.

With relocation to RAM this is no longer needed.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoTI814x : Updated the DDR DMM_LISA_MAP config for ti8148
Raj, Deepu [Fri, 24 Jun 2011 12:13:36 +0000 (17:43 +0530)]
TI814x : Updated the DDR DMM_LISA_MAP config for ti8148

 ti8148 DDR is configured to 128-byte interleaved mode having
 two 512MB sections for PG2.1 and two 256MB sections with a
 memory hole in between for PG1.0

7 years agoTI816x : Updated the DDR DMM_LISA_MAP config for ti8168
Raj, Deepu [Thu, 23 Jun 2011 13:57:58 +0000 (19:27 +0530)]
TI816x : Updated the DDR DMM_LISA_MAP config for ti8168

ti8168 DDR is configured to 128-byte interleaved mode having
two 512MB sections

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
7 years agoTI814X : Aligned the PLL values to PG2.1 v4 GEL file
Raj, Deepu [Thu, 23 Jun 2011 12:16:13 +0000 (17:46 +0530)]
TI814X : Aligned the PLL values to PG2.1 v4 GEL file

Updated the IVA,DSS,ISS,AUDIO pll to the latest gel file

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
7 years agoti8148: cust : modify the cpsw PHY address for new EVM
Sriramakrishnan A G [Wed, 22 Jun 2011 12:13:28 +0000 (17:43 +0530)]
ti8148: cust : modify the cpsw PHY address for new EVM

On the new EVM the PHY address are interchanged. revert this
patch once the issue is handled through board modification

Signed-off-by: Sriramakrishnan A G <srk@ti.com>
7 years agomiiphyutil: (hack) Disable check for 1000BaseX
Sriramakrishnan A G [Wed, 22 Jun 2011 12:14:53 +0000 (17:44 +0530)]
miiphyutil: (hack) Disable check for 1000BaseX

Atheros PHY reports 1000BaseX incorrectly. Add hack to
disable check for 1000BaseX mode.

Signed-off-by: Sriramakrishnan A G <srk@ti.com>
7 years agoti8148: cpsw : add support for rgmii
Sriramakrishnan A G [Wed, 22 Jun 2011 12:10:00 +0000 (17:40 +0530)]
ti8148: cpsw : add support for rgmii

Added pin-mux and clock configuration to support
rgmii interface on newer EVM(ES2.1)

Signed-off-by: Sriramakrishnan A G <srk@ti.com>
7 years agoti8148 cpsw : add pin mux configuration for second switch port.
Sriramakrishnan A G [Thu, 31 Mar 2011 14:38:26 +0000 (20:08 +0530)]
ti8148 cpsw : add pin mux configuration for second switch port.

Signed-off-by: Sriramakrishnan A G <srk@ti.com>
7 years agoTI814X : Applied the new SW_LEVEL param for DDR3 @400MHz
Raj, Deepu [Wed, 22 Jun 2011 14:25:37 +0000 (19:55 +0530)]
TI814X : Applied the new SW_LEVEL param for DDR3 @400MHz

 updated the default DDR freq to 400MHz for ti8148 PG2.1
 alone with the new SW_LEVEL values

Signed-off-by: Raj, Deepu <deepu.raj@ti.com>
7 years agoTI816X : Set default TI8168 DDR3 Frq to 800MHz
Raj, Deepu [Tue, 14 Jun 2011 09:05:19 +0000 (14:35 +0530)]
TI816X : Set default TI8168 DDR3 Frq to 800MHz

 Modifed the "#define DDR_PLL_796" to set the
 default DDR3 to 800MHz.

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X : code cleanup for ti814x DDR settings in ddr_defs.h
Raj, Deepu [Tue, 14 Jun 2011 07:10:51 +0000 (12:40 +0530)]
TI814X : code cleanup for ti814x DDR settings in ddr_defs.h

 Reorganised all ti8148 ddr related code in ddr_defs.h
 under the CONFIG_TI8148 macro

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X : code cleanup for ti814x DDR settings in ddr_defs.h
Raj, Deepu [Mon, 13 Jun 2011 12:27:53 +0000 (17:57 +0530)]
TI814X : code cleanup for ti814x DDR settings in ddr_defs.h

Reorganised all ti8148 ddr related code in ddr_defs.h
under the CONFIG_TI8148_EVM macro

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X: Fixed CPU revision printing for ti8148
Raj, Deepu [Thu, 9 Jun 2011 14:29:32 +0000 (19:59 +0530)]
TI814X: Fixed CPU revision printing for ti8148

 Modified print_cpuinfo() for ti8148.
 Added support for printing  unknown cpu rev.

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X : Added Support for printing cpu type and ARM Freq
Raj, Deepu [Wed, 8 Jun 2011 10:09:25 +0000 (15:39 +0530)]
TI814X : Added Support for printing cpu type and ARM Freq

 Enabled the printing of cpu type and ARM/DDR frequency
 for ti8148. get_cpu_type() will return b8f2 for ti8148.

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X : fixed PG detect for PG2.1 EVM's having 0xc chip rev
Raj, Deepu [Wed, 8 Jun 2011 05:04:28 +0000 (10:34 +0530)]
TI814X : fixed PG detect for PG2.1 EVM's having 0xc chip rev

get_cpu_rev() will return PG2_1 if it reads both 0xc and 0x3
due to the wrong 0xc value efused in some PG2.1 devices

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X : Modified DDR2/DDR3 Selection using PG rev
Raj, Deepu [Tue, 7 Jun 2011 10:19:52 +0000 (15:49 +0530)]
TI814X : Modified DDR2/DDR3 Selection using PG rev

PG1.0 will always use DDR2 and PG2.1 uses DDR3 by default
Use "#define CONFIG_TI814X_EVM_DDR2" to enable DDR2 for PG2.1

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X: Code cleanup and MODENA_N value fixed
Deepu Raj [Wed, 25 May 2011 09:43:28 +0000 (15:13 +0530)]
TI814X: Code cleanup and MODENA_N value fixed

Basic code cleanup and modified the value
for MODENA_ N divider value from 0x10001 to 0x1

Signed-off-by: Deepu Raj <x0159681@ti.com>
7 years agoTI814X: Explicitly put PLL in bypass mode before configuring.
Basheer, Mansoor Ahamed [Wed, 18 May 2011 07:23:18 +0000 (12:53 +0530)]
TI814X: Explicitly put PLL in bypass mode before configuring.

 ADPLLJ is put explicitly in by-pass mode before changing the
 configuration.

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
7 years agoTI814X: Enable Runtime PG detection by default.
Basheer, Mansoor Ahamed [Tue, 17 May 2011 06:37:20 +0000 (12:07 +0530)]
TI814X: Enable Runtime PG detection by default.

get_cpu_rev() will return PG2_1 if it reads 0x3
and for rest all  it will return PG1_0

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X: IVA, ISS, USB PLL configuration for PG2x.
Basheer, Mansoor Ahamed [Mon, 16 May 2011 08:44:51 +0000 (14:14 +0530)]
TI814X: IVA, ISS, USB PLL configuration for PG2x.

 Enabled IVA, ISS, DSP PLL configuration for PG2x.
 Runtime values for configuring these ppl values based on PG
 using pg_val_ti814x() function

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI814X: PG2.x support with DDR3
Basheer, Mansoor Ahamed [Thu, 12 May 2011 12:04:52 +0000 (17:34 +0530)]
TI814X: PG2.x support with DDR3

 Added support for PG2.x with DDR3 support.
 Add helper functions for configuring DDR PHY data and command macro and
 and cleaned some code for improper usage of blank spaces.

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI81XX: Fix get_cpu_rev() to mask only 4-bit
Basheer, Mansoor Ahamed [Thu, 12 May 2011 10:32:16 +0000 (16:02 +0530)]
TI81XX: Fix get_cpu_rev() to mask only 4-bit

 Chip revision is only 4-bit. Hence mask only 4-bit.

Signed-off-by: Basheer, Mansoor Ahamed <mansoor.ahamed@ti.com>
7 years agoTI816x : PG rutime detection for DDR2 EMIF CFG value
Deepu Raj [Thu, 2 Jun 2011 11:50:16 +0000 (17:20 +0530)]
TI816x : PG rutime detection for DDR2 EMIF CFG value

 Added the rumetime detection support for configure
 the EMIF_CFG value for PG 1.0 and 1.1 DDR2

Signed-off-by: Raj, Deepu <x0159681@ti.com>
7 years agoTI816X: FAPLL configurations for DDR 675MHz
Anil Kumar Ch [Thu, 19 May 2011 06:35:33 +0000 (12:05 +0530)]
TI816X: FAPLL configurations for DDR 675MHz

This patch corrects divider values which are used in FAPLL
configuration for DDR3 675MHz frequency.

Signed-off-by: Anil Kumar Ch <anilkumar@ti.com>
7 years agoti814x: Simplify the ARM frequency calculation
Vaibhav Bedia [Fri, 6 May 2011 10:49:46 +0000 (16:19 +0530)]
ti814x: Simplify the ARM frequency calculation

Instead of the hack used for ARM frequency, simplify the logic
and make the procedure consistent with the rest of the code.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Explicitly set oscillator sources
Vaibhav Bedia [Thu, 28 Apr 2011 08:33:27 +0000 (14:03 +0530)]
ti814x: Explicitly set oscillator sources

Even though the default values are correct, set the
oscillator source for L3 and Audio PLL to avoid any issues.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Update IVA PLL config
Vaibhav Bedia [Wed, 27 Apr 2011 12:14:07 +0000 (17:44 +0530)]
ti814x: Update IVA PLL config

Modify the IVA PLL config to get an output of 320Mhz.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Remove DSS PLL config
Vaibhav Bedia [Wed, 27 Apr 2011 12:09:18 +0000 (17:39 +0530)]
ti814x: Remove DSS PLL config

DSS PLL configuration is to be handled by the video driver.
To avoid any conflicts, remove the code for the same from U-Boot.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Update DMM LISA mapping for interleaving
Vaibhav Bedia [Wed, 27 Apr 2011 06:28:44 +0000 (11:58 +0530)]
ti814x: Update DMM LISA mapping for interleaving

The current setup gives the following memory map
0x80000000-0x8FFFFFFF: 256MB interleaved to EMIF0/1 128 byte boundary
0xC0000000-0xCFFFFFFF: 256MB interleaved to EMIF0/1 128 byte boundary

Note: Any access to the unmapped region without error handling will result in
a system hang.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Update DDR2/3 controller PHY register
Vaibhav Bedia [Wed, 27 Apr 2011 05:30:24 +0000 (11:00 +0530)]
ti816x: Update DDR2/3 controller PHY register

Make RD_ODT 50 Ohms

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoFor OMAP36xx move sys_clk to 26MHz
Vaibhav Hiremath [Fri, 8 Apr 2011 20:30:40 +0000 (02:00 +0530)]
For OMAP36xx move sys_clk to 26MHz

Also change DPLL4 setting to 26MHz sys_clk

7 years agoomap3evm/beagle/am3517evm:Change the console port to right value
Vaibhav Hiremath [Fri, 8 Apr 2011 13:24:52 +0000 (18:54 +0530)]
omap3evm/beagle/am3517evm:Change the console port to right value

OMAP3EVM: ttyS2 => ttyO0
AM3517EVM: ttyS2 => ttyO2
Beagle: ttyS2 => ttyO2

7 years agoomap3_evm: Change ttyS2 => ttyO0
Vaibhav Hiremath [Fri, 8 Apr 2011 13:24:17 +0000 (18:54 +0530)]
omap3_evm: Change ttyS2 => ttyO0

7 years agoOMAP3: NAND: Setting default ECC scheme as 1-bit hw (Kernel/FS layout)
Parth Mauria Saxena [Mon, 28 Mar 2011 10:14:31 +0000 (15:44 +0530)]
OMAP3: NAND: Setting default ECC scheme as 1-bit hw (Kernel/FS layout)

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
7 years agoOMAP3: NAND: Fixing a few prints
Parth Mauria Saxena [Fri, 25 Mar 2011 13:25:09 +0000 (18:55 +0530)]
OMAP3: NAND: Fixing a few prints

Changing from 1-bit sw ecc to 1-bit hw ecc for Uboot

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
7 years agoOMAP3: NAND: Fixing a few prints
Parth Mauria Saxena [Thu, 24 Mar 2011 06:49:25 +0000 (12:19 +0530)]
OMAP3: NAND: Fixing a few prints

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
7 years agoremove build warning
Abhilash Vadakkepat Koyamangalath [Wed, 23 Mar 2011 12:45:41 +0000 (18:15 +0530)]
remove build warning

This patch resolves the following build warning:
    beagle.c: In function 'misc_init_r':
    beagle.c:130: warning: implicit declaration of function
'twl4030_pmrecv_vsel_cfg'

7 years agoremove build warnings This patch removes the following build warnings: am3517evm...
Abhilash Vadakkepat Koyamangalath [Wed, 23 Mar 2011 12:40:01 +0000 (18:10 +0530)]
remove build warnings This patch removes the following build warnings: am3517evm.c: In function 'misc_init_r': am3517evm.c:80: warning: implicit declaration of function 'omap_request_gpio' am3517evm.c:81: warning: implicit declaration of function 'omap_set_gpio_direction' am3517evm.c:82: warning: implicit declaration of function 'omap_set_gpio_dataout' am3517evm.c: In function 'cpu_eth_init': am3517evm.c:117: warning: implicit declaration of function 'davinci_emac_initialize'

7 years agoremove omap3 common build warnings
Abhilash Vadakkepat Koyamangalath [Wed, 23 Mar 2011 12:23:02 +0000 (17:53 +0530)]
remove omap3 common build warnings

This patch resolves the following build warnings:
    omap_bch_decoder.c:399: warning: data definition has no
type or storage class
    omap_bch_decoder.c:399: warning: type defaults to 'int'
in declaration of 'EXPORT_SYMBOL'
    omap_bch_decoder.c:399: warning: parameter names (without
 types) in function declaration
    omap_gpmc.c: In function 'omap_nand_switch_ecc':
    omap_gpmc.c:267: warning: enumeration value 'NAND_ECC_NONE'
 not handled in switch
    omap_gpmc.c:267: warning: enumeration value
'NAND_ECC_HW_SYNDROME' not handled in switch
    omap_gpmc.c:267: warning: enumeration value
'NAND_ECC_HW_OOB_FIRST' not handled in switch

7 years agoOMAP3: NAND: Restricting 4,8 bit BCH ECC schemes only for OMAP platforms
Parth Mauria Saxena [Tue, 22 Mar 2011 07:25:33 +0000 (12:55 +0530)]
OMAP3: NAND: Restricting 4,8 bit BCH ECC schemes only for OMAP platforms

This patch is to restrict OMAP platform specific code; needs to move to
OMAP board specific file.

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
7 years agoOMAP3: NAND: Synching 1b-hw ecc schemes with 1b-sw, 4b and 8b ecc schemes
Parth Mauria Saxena [Mon, 21 Mar 2011 11:16:15 +0000 (16:46 +0530)]
OMAP3: NAND: Synching 1b-hw ecc schemes with 1b-sw, 4b and 8b ecc schemes

This patch merges the two variants of 1 bit hw ecc (one for xloader
and other for uboot, kernel and file system) with the othee ecc schemes
(1 bit sw ecc, 4 bit ecc, 8 bit ecc)

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
7 years agoChanges to support 2 diff hw ECC modes of operation on the u-boot cmd line: value...
Abhilash Vadakkepat Koyamangalath [Sat, 15 Jan 2011 14:02:53 +0000 (19:32 +0530)]
Changes to support 2 diff hw ECC modes of operation on the u-boot cmd line: value 1: for uboot/kernel/FS layouts(default) [NEW] - ECC position starts from byte 40 onwds value 2: for x-load layouts - ECC position starts from byte 2 onwds

7 years agoUboot BCH 4b8b Error Correction
Greg Guyotte [Mon, 21 Feb 2011 14:01:56 +0000 (19:31 +0530)]
Uboot BCH 4b8b Error Correction

* Error correction mode controlled by U-boot 'nandecc' command.
* 'nandecc' options are hw/sw/bch4_sw/bch8_sw.
* Default mode is 4BIT error correction (set in board_nand_init()).

Signed-off-by: Parth Mauria Saxena <parth.saxena@ti.com>
Signed-off-by: Greg Guyotte <gguyotte@ti.com>
7 years agoam3517evm: Disable CFI flash support from default config
Vaibhav Hiremath [Sat, 19 Mar 2011 09:18:36 +0000 (14:48 +0530)]
am3517evm: Disable CFI flash support from default config

Since NOR Flash is only available on AM3517 Application board,
and including CFI flash support in default config leads to boot failure
on non-application board usecase.

So disable NOR flash support in default config, let user select this
manually.

7 years agogpmc init: clear irq_enable for CS0 for all boot modes
Vaibhav Hiremath [Thu, 17 Mar 2011 17:40:26 +0000 (23:10 +0530)]
gpmc init: clear irq_enable for CS0 for all boot modes

This is especially required on AM3517, where we have NOR Flash support.
On AM3517, we have HW issue where to get NOR boot mode we need do some board
modification which disconnects permanant NAND<->CS0 link and allows selection
via Apps board and Baseboard switches. Having said that, gpmc_wait0 signal
still stays connected to NAND flash irrespective of whether CS0 is interfaced
to NOR or NAND.
In addition to this, in case of NOR flash boot, kernel does request_irq and due
to this board issue we get contigious interrupt from NAND (gpmc_wait0).

The workaround for this is, clear irq_enable register in U-boot itself for all
boot modes.

7 years agoAM3517: Add NOR Flash boot mode Support
Vaibhav Hiremath [Thu, 17 Mar 2011 12:57:46 +0000 (18:27 +0530)]
AM3517: Add NOR Flash boot mode Support

Please note that NOR Flash is located on Application board and requires
hardware modification to get NOR boot mode working.

NOR Flash boot mode configuration -

        - From SOM board remove R235 register.
- Set switch S11.3 position to "ON"
- Set S7 switch position to
 1  2   3   4   5
 -----------------
on off off off off

Please note that, once you remove R235 register from SOM board, you will
not be able to boot from NAND without Application board.
The GPMC_nCS0 is now routed thorugh Application board.

Please note that, <Rev4 revision of Application board doesn't
work with NOR Flash due to HW issue.

7 years agoBeagleXM: Configure drive strength to 20 ohms/8ma
Jason Kridner [Wed, 23 Feb 2011 08:36:34 +0000 (14:06 +0530)]
BeagleXM: Configure drive strength to 20 ohms/8ma

Bus capacitance has to be adjusted for pull up registers
on i2c bus having sensor connected to it.
for more details refer:
http://focus.ti.com/lit/ug/spruf98m/spruf98m.pdf, page 2765

7 years agoti816x: Modify the default configuration for DDR3
Vaibhav Bedia [Tue, 15 Feb 2011 12:04:10 +0000 (17:34 +0530)]
ti816x: Modify the default configuration for DDR3

Make the default build for DDR3 @ 400MHz.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Modify frequency calculation for printing
Rajkumar.R [Mon, 14 Feb 2011 15:30:18 +0000 (21:00 +0530)]
ti816x: Modify frequency calculation for printing

This patch modifies the formula for frequency calculation
to take care of overflow conditions.

Signed-off-by: Rajkumar.R <x0154572@ti.com>
7 years agoti8168: Change the default config for DDR3
Vaibhav Bedia [Thu, 10 Feb 2011 14:41:28 +0000 (20:11 +0530)]
ti8168: Change the default config for DDR3

Make the default configuration for DDR3 @ 796MHz.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Fix initialization of DMTIMER1 clock source
Brad Griffis [Fri, 28 Jan 2011 21:54:38 +0000 (15:54 -0600)]
ti814x: Fix initialization of DMTIMER1 clock source

This patch fixes the issue with selection of clk src for
the DMTIMERs.

Signed-off-by: Brad Griffis <bgriffis@ti.com>
7 years agoti8148: Add the 2nd stage bootcmd
Vaibhav Bedia [Wed, 19 Jan 2011 14:16:28 +0000 (19:46 +0530)]
ti8148: Add the 2nd stage bootcmd

This patch adds the 2nd bootcmd to execute a script from MMC/SD card

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti81xx: Add support for echo command
Vaibhav Bedia [Wed, 12 Jan 2011 13:45:04 +0000 (19:15 +0530)]
ti81xx:  Add support for echo command

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: MMC/SD: Update pad config
Vaibhav Bedia [Wed, 12 Jan 2011 13:36:45 +0000 (19:06 +0530)]
ti814x: MMC/SD: Update pad config

This patch updates the MMC/SD pad config to make the signal pull-down by default.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Print a message from 1st stage before loading 2nd stage
Vaibhav Bedia [Mon, 10 Jan 2011 15:22:49 +0000 (20:52 +0530)]
ti814x: Print a message from 1st stage before loading 2nd stage

To avoid confusion about the 2 stages add a print to indicate
the expected behavior of the 1st stage.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Ascii art
Vaibhav Bedia [Mon, 10 Jan 2011 14:37:28 +0000 (20:07 +0530)]
ti814x: Ascii art

Ascii art for ti814x :)

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Enable hush parser
Vaibhav Bedia [Mon, 10 Jan 2011 14:35:20 +0000 (20:05 +0530)]
ti814x: Enable hush parser

Hush parser will be needed for parsing the commands
in a boot script which are typically read from SD cards.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Fix MMC1 CLK_CTRL register
Vaibhav Bedia [Mon, 10 Jan 2011 10:53:21 +0000 (16:23 +0530)]
ti814x: Fix MMC1 CLK_CTRL register

The CLK_CTRL register used for enabling MMC1 was incorrect.
This created a dependency on the ROM code for correctly enabling
the MMC1 module.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Update L3 config for 220MHz
Vaibhav Bedia [Fri, 7 Jan 2011 10:47:55 +0000 (16:17 +0530)]
ti814x: Update L3 config for 220MHz

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Delay mux setup after relocation to DDR
Vaibhav Bedia [Fri, 7 Jan 2011 07:02:56 +0000 (12:32 +0530)]
ti814x: Delay mux setup after relocation to DDR

With the recent change to make even the 1st stage of U-Boot
relocate to DDR, mux setup should be done after relocation to DDR
has been done.

Issue root-caused and fixed by Brad Griffins.

Signed-off-by: Brad Griffins <bgriffins@ti.com>
Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Fix M2NDIV register value for Modena PLL
Vaibhav Bedia [Fri, 7 Jan 2011 05:55:04 +0000 (11:25 +0530)]
ti814x: Fix M2NDIV register value for Modena PLL

With the previous value, post divider M2 will be 0 which is incorrect.
Explicitly set the M2 value to 1 to avoid issues.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Add Audio PLL setup code
Vaibhav Bedia [Fri, 7 Jan 2011 05:43:18 +0000 (11:13 +0530)]
ti814x: Add Audio PLL setup code

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Add DSP PLL setup code
Vaibhav Bedia [Fri, 7 Jan 2011 05:38:42 +0000 (11:08 +0530)]
ti814x: Add DSP PLL setup code

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Add DSS PLL setup code
Vaibhav Bedia [Fri, 7 Jan 2011 05:35:45 +0000 (11:05 +0530)]
ti814x: Add DSS PLL setup code

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoTI81XX: NAND: Setting 1-bit Hamming code H/W ECC as default ECC scheme. master
Mansoor Ahamed [Thu, 16 Dec 2010 08:32:57 +0000 (14:02 +0530)]
TI81XX: NAND: Setting 1-bit Hamming code H/W ECC as default ECC scheme.

  - Now all partitions in the NAND will use 1-bit H/W ECC as default.
    This includes ENV, Kernel, Filesystem.
  - NAND partition which has the u-boot image will still use H/W BCH-8

Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com>
7 years agoti816x: WDT support
Vaibhav Bedia [Wed, 15 Dec 2010 15:01:18 +0000 (20:31 +0530)]
ti816x: WDT support

This patch adds *basic* WDT support for TI8168 EVM.
Currently the watchdog is just stopped and then unfrozen.

After this the kernel driver can use the watchdog normally.

Note: Proper use of WDT requires a board modification to be
done on the TI8168 EVM.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoTI81XX: NAND: Change oob layout to synch with kernel
Parth Mauria Saxena [Tue, 14 Dec 2010 12:55:47 +0000 (18:25 +0530)]
TI81XX: NAND: Change oob layout to synch with kernel

This patch changes the oob layout in uboot for 1 bit hamming code
and makes it in synch with the kernel

Signed-off-by: Parth Mauria Saxena <a0131646@psplinux052.india.ti.com>
7 years agoti814x: Add IVA PLL setup code
Vaibhav Bedia [Fri, 10 Dec 2010 06:15:57 +0000 (11:45 +0530)]
ti814x: Add IVA PLL setup code

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Add ISS PLL configuration
Hemant Pedanekar [Wed, 24 Nov 2010 11:10:36 +0000 (16:40 +0530)]
ti814x: Add ISS PLL configuration

Add ISS PLL configuration as required for Ducati MMU access.

Note that, at present, trim values are not configured.

Signed-off-by: Hemant Pedanekar <hemantp@ti.com>
7 years agoti816x: Fix compiler warning
Vaibhav Bedia [Thu, 9 Dec 2010 14:28:34 +0000 (19:58 +0530)]
ti816x: Fix compiler warning

TBM with DDR3 support patch

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: TBM with initial commit for ti814x
Vaibhav Bedia [Thu, 9 Dec 2010 12:20:41 +0000 (17:50 +0530)]
ti814x: TBM with initial commit for ti814x

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoTI8168: fix handling of ethernet mac address.
Sriramakrishnan [Wed, 8 Dec 2010 14:26:02 +0000 (19:56 +0530)]
TI8168: fix handling of ethernet mac address.

With this change, the init code will fetch mac address from
env space. If it returns empty, will look for MAC address from
Control register space(e-fuse).

If you are setting ethaddr using setenv/saveenv commands, the
new MAC address will take effect on subsequent reboot only.

Signed-off-by: Sriramakrishnan <srk@ti.com>
7 years agoTI EMAC driver : Add gigabit mode support
Sriramakrishnan [Wed, 8 Dec 2010 14:26:02 +0000 (19:56 +0530)]
TI EMAC driver : Add gigabit mode support

This patch adds support for gigabit mode of operation

Signed-off-by: Sriramakrishnan <srk@ti.com>
7 years agoOMAP:I2C: Fixed build error/warning
Vaibhav Hiremath [Tue, 30 Nov 2010 08:09:08 +0000 (13:39 +0530)]
OMAP:I2C: Fixed build error/warning

Following commit breaks the OMAP3 build,

Commit ID - 927057f10a01323abb4400a7ed356058b0c5d3b7
Subject - ti81xx: I2C support

7 years agoti8148: Skip pcie_pll config
Vaibhav Bedia [Tue, 7 Dec 2010 09:52:43 +0000 (15:22 +0530)]
ti8148: Skip pcie_pll config

Currently pcie pll configuration is not done from U-Boot

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: NOR boot support config option
Vaibhav Bedia [Tue, 7 Dec 2010 12:52:23 +0000 (18:22 +0530)]
ti816x: NOR boot support config option

Add NOR boot support config option to the Makefile

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8148: Size reduction config options... revisit
Vaibhav Bedia [Tue, 7 Dec 2010 10:06:23 +0000 (15:36 +0530)]
ti8148: Size reduction config options... revisit

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8148: Reorg of config options
Vaibhav Bedia [Tue, 7 Dec 2010 10:05:48 +0000 (15:35 +0530)]
ti8148: Reorg of config options

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8148: Minor change in board file
Vaibhav Bedia [Tue, 7 Dec 2010 10:02:51 +0000 (15:32 +0530)]
ti8148: Minor change in board file

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8168: Update config name for selecting ENV support
Vaibhav Bedia [Tue, 7 Dec 2010 09:25:30 +0000 (14:55 +0530)]
ti8168: Update config name for selecting ENV support

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8148: Update config name for selecting ENV support
Vaibhav Bedia [Tue, 7 Dec 2010 09:24:16 +0000 (14:54 +0530)]
ti8148: Update config name for selecting ENV support

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti8148: Rename config names used in Makefile and config file
Vaibhav Bedia [Tue, 7 Dec 2010 09:20:35 +0000 (14:50 +0530)]
ti8148: Rename config names used in Makefile and config file

Rename the config names to easily differentiate between the config
options for an image

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: SD support
Vaibhav Bedia [Fri, 26 Nov 2010 08:40:38 +0000 (14:10 +0530)]
ti814x: SD support

This patch adds SD support to ti814x. A two stage approach is adopted
for SD boot since the 1st stage size is limited to 110KB.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Config file clean-up
Vaibhav Bedia [Fri, 26 Nov 2010 08:38:46 +0000 (14:08 +0530)]
ti814x: Config file clean-up

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Makefile clean-up
Vaibhav Bedia [Fri, 26 Nov 2010 07:22:13 +0000 (12:52 +0530)]
ti814x: Makefile clean-up

Reorg of ti814x options in Makefile

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti814x: Diable cache for now
Vaibhav Bedia [Fri, 26 Nov 2010 07:07:01 +0000 (12:37 +0530)]
ti814x: Diable cache for now

Issues seen when cache is enabled and 2nd stage loaded from SD
Disabling cache for now

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Default build for DDR2 @ 400MHz I/O clock
Vaibhav Bedia [Thu, 11 Nov 2010 11:42:59 +0000 (17:12 +0530)]
ti816x: Default build for DDR2 @ 400MHz I/O clock

The default configuration will be for DDR2 with the
I/O clock @ 400MHz

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Support for DDR3 at different frequencies
Vaibhav Bedia [Wed, 29 Sep 2010 15:08:52 +0000 (20:38 +0530)]
ti816x: Support for DDR3 at different frequencies

- This patch adds support for DDR3 at different frequencies on PG1.1 samples
 - Supported frequencies for DDR3: 400, 531, 675 and 796 MHz
 - Currently software leveling approach is used for DDR3 init
 - The ROM code bug which causes SYSCLK10 to run at half the expected frequency
   is now fixed by changing the PRCM divider instead of DDRPLL_MDIV2
 - Code for changing the core voltage to 1V via GPIOs is also added in lowlevel init

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Support for boot script for setting ENV
Vaibhav Bedia [Wed, 13 Oct 2010 05:36:57 +0000 (11:06 +0530)]
ti816x: Support for boot script for setting ENV

This patch enables support for executing a script stored in MMC/SD card
to set ENV variables.This is necessary for systems which have no flash storage
and ENV needs to be set without rebuilding U-Boot binary with hardcoded values.

To generate the script named boot.scr create a file boot.txt with the normal
U-Boot commands for setting ENV. Eg: setenv bootcmd 'dhcp; tftp; bootm'

Then use mkimage utility (./u-boot/tools/mkimage) in the following manner:
mkimage -A arm -O linux -C none -name script -d boot.txt boot.scr

Copy this file to the FAT partition on the MMC/SD card and let the system boot.

Note: The script will be executed automatically in case there is no flash storage
or if nothing has been saved to the ENV section of the flash.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoSuppress CPUINFO printing in 1st stage of SD
Vaibhav Bedia [Wed, 6 Oct 2010 10:40:40 +0000 (16:10 +0530)]
Suppress CPUINFO printing in 1st stage of SD

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Change 2nd stage load address for SD boot
Vaibhav Bedia [Wed, 6 Oct 2010 09:56:53 +0000 (15:26 +0530)]
ti816x: Change 2nd stage load address for SD boot

In case of SD boot the 2nd stage will get transferred
to DDR_START + 8MB

Note, the first stage has a big bss section. So if the 2nd
stage is read close to the start of 1st stage, fatload
will hang.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Change TEXT_BASE
Vaibhav Bedia [Wed, 6 Oct 2010 09:50:52 +0000 (15:20 +0530)]
ti816x: Change TEXT_BASE

To avoid issues with larger kernel images change the TEXT_BASE
to leave a space of 7MB on top.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Add target which runs out of internal memory
Vaibhav Bedia [Sun, 3 Oct 2010 19:32:14 +0000 (01:02 +0530)]
ti816x: Add target which runs out of internal memory

Having a minimal build which runs out of internal memory
is useful in debugging DDR related issues of EVMs.

This patch adds a new target name "ti8168_evm_min_ocmc"
which serves this purpose.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Change the location of config.tmp inclusion
Vaibhav Bedia [Sun, 3 Oct 2010 19:29:07 +0000 (00:59 +0530)]
ti816x: Change the location of config.tmp inclusion

Including config.tmp at the end of config.mk helps
in over-riding variables/macros selectively

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti81xx: Suppress debug prints on console
Vaibhav Bedia [Sun, 3 Oct 2010 19:27:42 +0000 (00:57 +0530)]
ti81xx: Suppress debug prints on console

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti81xx: Add cpu type and rev detection logic
Vaibhav Bedia [Wed, 29 Sep 2010 11:50:26 +0000 (17:20 +0530)]
ti81xx: Add cpu type and rev detection logic

This patch adds the logic for cpu type and rev detection
for the ti81xx family

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
7 years agoti816x: Additional spacing in config file for readability
Vaibhav Bedia [Sat, 18 Sep 2010 13:36:21 +0000 (19:06 +0530)]
ti816x: Additional spacing in config file for readability

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>